CS4202
AC ’97 SERIAL PORT TIMING
Standard test conditions unless otherwise noted: T
ambient
= 25° C,
AVdd = 5.0 V, DVdd = 3.3 V; C
L
= 55 pF load.
Parameter
RESET Timing
RESET# active low pulse width
RESET# inactive to BIT_CLK start-up delay
Symbol
T
rst_low
T
rst2clk
Min
1.0
-
-
-
-
100
-
-
-
36
36
-
-
-
-
8
10
0
2
2
2
2
-
1.0
162.8
15
-
Typ
-
4.0
4.0
2.5
62.5
-
12.288
81.4
-
40.7
40.7
48
20.8
1.3
19.5
10
-
-
-
-
4
4
0.285
-
285
-
-
Max
-
-
-
-
-
-
-
-
750
45
45
-
-
-
-
12
-
-
6
6
6
6
1.0
-
-
-
25
Unit
µs
µs
µs
ms
µs
µs
MHz
ns
ps
ns
ns
kHz
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
(XTL mode)
(OSC mode)
(PLL mode)
1st SYNC active to CODEC READY ‘set’
Vdd stable to RESET# inactive
Clocks
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter (depends on XTL_IN source)
BIT_CLK high pulse width
BIT_CLK low pulse width
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
Data Setup and Hold
Output propagation delay from rising edge of BIT_CLK
Input setup time from falling edge of BIT_CLK
Input hold time from falling edge of BIT_CLK
Input signal rise time
Input signal fall time
Output signal rise time
(Note 4)
Output signal fall time
(Note 4)
Misc. Timing Parameters
End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)
SYNC pulse width (PR4) Warm Reset
SYNC inactive (PR4) to BIT_CLK start-up delay
Setup to trailing edge of RESET# (ATE test mode) (Note 4)
Rising edge of RESET# to Hi-Z delay
(Note 4)
T
sync2crd
T
vdd2rst#
F
clk
T
clk_period
T
clk_high
T
clk_low
F
sync
T
sync_period
T
sync_high
T
sync_low
T
co
T
isetup
T
ihold
T
irise
T
ifall
T
orise
T
ofall
T
s2_pdown
T
sync_pr4
T
sync2clk
T
setup2rst
T
off
DS549PP2
9
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