CS42438-CMZ 参数 Datasheet PDF下载

FS is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data

sample and must be held valid for at least 1 SCLK period.

NOTE: The ADC does not meet the timing requirements for proper operation in Quad-Speed

Mode.

256 clks

FS

SCLK

DAC_SDIN

LSB MSB

Bit or Word Wide

LSB MSB

LSB MSB

AOUT2

LSB MSB

AOUT3

LSB MSB

AOUT4

LSB MSB

LSB MSB

LSB MSB

LSB MSB

AOUT1

32 clks

ADC_SDOUT

MSB

AIN1

32 clks

AOUT5

AOUT6

AOUT7

AOUT8

32 clks

32 clks

32 clks

32 clks

32 clks

32 clks

32 clks

LSB MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

AIN2

32 clks

AIN3

32 clks

AIN4

32 clks

AIN5

32 clks

AIN6

32 clks

AUX1

32 clks

AUX2

32 clks

Figure 14. TDM Serial Audio Format

5.5.2 I/O Channel Allocation

Digital

Input/Output

DAC_SDIN

ADC_SDOUT

Interface

Format

TDM

TDM

Analog Output/Input Channel Allocation

from/to Digital I/O

AOUT 1,2,3,4,5,6,7,8

AIN 1,2,3,4,5,6; (2 additional channels from AUX_SDIN)

Table 6. Serial Audio Interface Channel Allocations

34

DS646PP2