EP7311
High-Performance, Low-Power System on Chip
CODEC Interface
The EP7311 includes an interface to telephony-type CODECs
for easy integration into voice-over-IP and other voice
communications systems. The CODEC interface is
multiplexed to the same pins as the MCP and SSI2.
Pin Mnemonic
PCMCLK
PCMOUT
PCMIN
PCMSYNC
Synchronous Serial Interface
•
•
ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)
Selectable serial clock polarity
I/O
O
O
I
O
Pin Description
Serial bit clock
Serial data out
Serial data in
Frame sync
Pin Mnemonic
ADCLK
ADCIN
ADCOUT
nADCCS
SMPCLK
I/O
O
I
O
O
O
Pin Description
SSI1 ADC serial clock
SSI1 ADC serial input
SSI1 ADC serial output
SSI1 ADC chip select
SSI1 ADC sample clock
Table F. CODEC Interface Pin Assignments
Note:
See
for information on pin
multiplexes.
Table H. Serial Interface Pin Assignments
LCD Controller
SSI2 Interface
An additional SPI/Microwire1-compatible interface is
available for both master and slave mode communications. The
SSI2 unit shares the same pins as the MCP and CODEC
interfaces through a multiplexer.
•
•
•
•
Synchronous clock speeds of up to 512 kHz
Separate 16 entry TX and RX half-word wide FIFOs
Half empty/full interrupts for FIFOs
Separate RX and TX frame sync signals for asymmetric
traffic
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The display
frame buffer start address is programmable, allowing the LCD
frame buffer to be in SDRAM, internal SRAM or external
SRAM.
•
•
•
•
Pin Mnemonic
SSICLK
SSITXDA
SSIRXDA
SSITXFR
SSIRXFR
I/O
I/O
O
I
I/O
I/O
Pin Description
Serial bit clock
Serial data out
Serial data in
Transmit frame sync
Receive frame sync
•
Interfaces directly to a single-scan panel monochrome STN
LCD
Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
Panel width size is programmable from 32 to 1024 pixels in
16-pixel increments
Video frame buffer size programmable up to
128 KB
Bits per pixel of 1, 2, or 4 bits
Pin Mnemonic
CL1
CL2
DD[3:0]
FRM
M
I/O
O
O
O
O
O
Pin Description
LCD line clock
LCD pixel clock out
LCD serial display data bus
LCD frame synchronization pulse
LCD AC bias drive
Table G. SSI2 Interface Pin Assignments
Note:
See
for information on pin
multiplexes.
Table I. LCD Interface Pin Assignments
8
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Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS506F1
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