2.0 Functional Description
CN8223
2.7 FIFO Port/UTOPIA Interface
ATM Transmitter/Receiver with UTOPIA Interface
Table 2-25. FIFO Receive Pin Descriptions
CN8223 FIFO Input
Functional Description
Receive Data Write Strobe
The receive data FIFO interface strobes data octets from FDAT_OUT[8:0] into an external
FIFO device on each rising edge of Receive Data Write Strobe. This strobe is a gated clock
with 48-, 52-, 53-, or 57- strobes for the corresponding number of cell octets, depending
on mode. There are four Receive Data Write Strobes, one per port.
Receive Data FIFO Full
This flag is active low. If Receive Data FIFO Full is asserted by the external FIFO and the
CN8223 attempts a write to that port data, loss occurs. If this happens, Receive FIFO Write
Error pin (FCTRL_OUT[10]) is asserted low. There are four Receive Data FIFO full signals,
one per port.
Receive Cell Sync Marker
The sync marker will be low during the last octet of data transfer and high during all other
octets of the data transfer for each cell regardless of the number of octets selected for
output.
Receive Cell Invalid Indication
This per-port signal indicates that a HEC or other check has failed. The invalid indication will
be low during the first octet of data transfer. If any enabled check fails, the invalid indication
will be high during the last five octets of the cell. If no failures occur, the indication will stay
de-asserted through the end of the cell. The FIFO or a microprocessor must mark this cell
as bad to prevent further processing.
Optional Start of Cell Mode
If Start-of-Cell/Write Error Output [bit 15] in the CELL_VAL register [0x14] is set, then
FCTRL_OUT[10] becomes an active-high start-of-cell output marker for the receiver, and
FCTRL_OUT[16] becomes an active-high start-of-cell output marker for the transmitter.
These indicators are valid only in 53-octet input/output mode. In this mode, the Receive
FIFO Write Error function is not available.
2.7.2 Transmit Port Priority Mechanism
Each of the four transmit data read ports has a priority level that is programmable
to four levels. The control bits for setting the port priority level are in the
CELL_GEN_x control registers. Priority level 0 is the highest priority, priority
level 3 is the lowest (see Table 2-26).
Table 2-26. Priority Levels
CELL_GEN 3
CELL_GEN 2
Priority Level
0
0
1
1
0
1
0
1
0
1
2
3
If more than one port is assigned the same priority level, then arbitration
occurs in port order with bandwidth allocated cyclically to Port 0, Port 1, Port 2,
and Port 3.
The priority state machine looks at the port empty flag inputs for all ports at
priority level 0 and reads cells from these ports cyclically until all port flags
indicate empty. If no cells are available at priority 0, the state machine then looks
at the port empty flags for all ports at priority level 1 and reads cells from these
ports cyclically as long as no priority 0 port has a cell ready.
2-40
Conexant
100046C
CONEXANT [ CONEXANT SYSTEMS, INC ]
