2
2.0 Functional Description
This chapter describes the CN8223 architecture and functional blocks. Figure 2-1
and Figure 2-2 illustrates detailed signal paths of the receiver and transmitter.
Figure 2-1. CN8223 Receiver Block Diagram
External
Framer
Mode
Clock, Sync, Serial Data
Serial
Bipolar
Data
Serial/
Parallel
DS-3/G.751
E3 Framer
Serial
MUX
MUX
NRZ
Data
Overhead Output
Enable
B3ZS/HDB3
STS-1/
STS-3c/
G.832
STS-1/
STS-3c/
STM-1
G.832
Octets
PLCP
STM-1
Framer
ATM
Cell
Receiver
Parallel Input
Octet, Clock
Serial/Parallel
Framer
MUX
MUX
HEC
Align.
Framer
100 Mbps
TAXI Interface
PHY
Mode
Alignment
Mode
Figure 2-2. CN8223 Transmitter Block Diagram
Serial/
Parallel
Data Out
ATM
DS3/
G.751 E3
Gen.
PLCP
Cell
B3ZS/
HDB3
Gen.
Gen.
MUX
MUX
Encode
STS-1/
STS-3c/
STM-1
G.832
Gen.
Overhead Input
100046C
Conexant
2-1
CONEXANT [ CONEXANT SYSTEMS, INC ]
