Bt8370/8375/8376
3.9 Performance Monitoring Registers
Fully Integrated T1/E1 Framer and Line Interface
3.9 Performance Monitoring Registers
Unused bits indicated by a dash (—) are reserved and should be written to 0. Writing to reserved bits has no
effect.
If the counter overflow interrupt [IER4; addr 00F] is enabled for the respective performance monitoring
counter, the counter rolls over after reaching its maximum count value. If the overflow interrupt is disabled, the
counter holds maximum value upon saturation. Refer to LATCH [addr 046] for a description of 1-second
latched counter operation. The processor must read the Least Significant Byte (LSB) before reading the Most
Significant Byte (MSB) of each multi-byte counter.
050—Framing Bit Error Counter LSB (FERR)
7
6
5
4
3
2
1
0
FERR[7]
FERR[6]
FERR[5]
FERR[4]
FERR[3]
FERR[2]
FERR[1]
FERR[0]
FERR[7:0]
Ft/Fs/T1DM/FPS/FAS Error Count
051—Framing Bit Error Counter MSB (FERR)
If LATCH_CNT [addr 046] is inactive, reading FERR [addr 051] clears the entire FERR[11:0] count value.
15
14
13
12
11
10
9
8
0
0
0
0
FERR[11]
FERR[10]
FERR[9]
FERR[8]
FERR[11:8]
Ft/Fs/T1DM/FPS/FAS Error Count
052—CRC Error Counter LSB (CERR)
7
6
5
4
3
2
1
0
CERR[7]
CERR[6]
CERR[5]
CERR[4]
CERR[3]
CERR[2]
CERR[1]
CERR[0]
CERR[7:0]
CRC6/CRC4 Error Count
3-58
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
