Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
3.14 Clock Rate Adapter Registers
3.14 Clock Rate Adapter Registers
Unused bits indicated by a dash (—) are reserved and should be written to 0. Writing to reserved bits has no
effect.
090—Clock Rate Adapter Configuration (CLAD_CR)
7
6
5
4
3
2
1
0
CEN
XSEL[2]
XSEL[1]
XSEL[0]
LFGAIN[3]
LFGAIN[2]
LFGAIN[1]
LFGAIN[0]
CEN
Enable CLAD Phase Detector—When active, the CPHASE detector compares the CLAD
reference (CLADI/RSCALE) to the CLAD variable (CLADV/VSCALE), and sends the
resulting phase error information to the NCO. When inactive, the CLADI signal is ignored and
JEN or JFREE [addr 002] selects the input timing reference.
CEN JEN JFREE JDIR
CLAD Input Timing Reference
0
0
0
1
1
1
X
0
REFCKI = Free running 10 MHz clock
REFCKI = Free running 10 MHz clock with transmit
JAT
0
1
1
1
REFCKI = Free running 10 MHz clock with receive
JAT
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
TXCLK = TCKI or ACKI per AISCLK [addr 068]
RXCLK = RPLL or RCKI per RDIGI [addr 020]
CLADI = System clock, bypass JAT elastic store
CLADI = System clock, with transmit JAT
CLADI = System clock, with receive JAT
X
0
1
NOTE: JCLK always operates at T1 or E1 line rate selected by T1/E1N.
XSEL[2:0]
Line Rate Multiple Select—The CLAD divider chain outputs (CLADO and CLADV) can be
programmed to operate at 20 to 23 times (1 X to 32 X) the T1/E1 line rate. XSEL chooses the
multiplier. This is applicable only when OSEL or VSEL [addr 091] selects the multiplier
output.
XSEL
Output (kHz)
T1/E1N = 0
Output (kHz)
T1/E1N = 1
Line Rate Multiplier
0
2048
4096
8192
16384
—
1544
3088
6176
12352
—
1X
2X
1
2
3
4X
8X
4, 5, 6, 7
Reserved
N8370DSE
Conexant
3-83
CONEXANT [ CONEXANT SYSTEMS, INC ]
