Bt8370/8375/8376
2.0 Circuit Description
2.4 Receiver
Fully Integrated T1/E1 Framer and Line Interface
2.4.4 Error Monitor
The following signal errors are detected in the RCVR: Frame Bit Error (FERR),
MFAS Error (MERR), CAS Error (SERR), CRC Error (CERR), and Pulse
Density Violations (PDVs). Each error type has an interrupt enable bit that allows
an interrupt to occur marking the event, and has an interrupt register bit read by
the interrupt service routine. All error status registers are reset on read unless the
LATCH_ERR bit is set in the Alarm/Error/Counter Latch Configuration register
[LATCH; addr 046]. LATCH_ERR enables the 1-second latching of alarms
coincident with the 1-second timer interrupt [ISR6; addr 005]. With
LATCH_ERR enabled, any error detected during the 1-second interval is latched
and held during the following 1-second interval. LATCH_ERR allows the
processor to gather error statistics based on the 1-second interval.
FERR is reported for the receive direction in the Error Interrupt Status register
[ISR5; addr 006] and for the transmit direction in Pattern Interrupt Status [ISR0;
addr 00B]. FERR indicates that 1 or more Ft/Fs/FPS frame bit errors or FAS
pattern errors occurred since the last time the interrupt status was read. The FERR
type is determined by the receive framer’s configuration [CR0; address 001].
While CRC4 framing is enabled, MERR is reported for the receive direction
in the Error Interrupt Status register [ISR5; addr 006] and for the transmit
direction in Pattern Interrupt Status [ISR0; addr 00B]. MERR is only applicable
in E1 mode and indicates that 1 or more MFAS pattern errors occurred since the
last time the interrupt status was read.
While CAS framing is enabled, SERR is reported for the receive direction in
the Error Interrupt Status register [ISR5; addr 006] and for the transmit direction
in Pattern Interrupt Status [ISR0; addr 00B]. SERR is applicable only in E1 mode.
In this mode, SERR indicates that 1 or more errors were received in the TS16
Multiframe Alignment Signal (MAS) since the last time the interrupt status was
read.
CERR is reported for the receive direction in the Error Interrupt Status register
[ISR5; addr 006] and for the transmit direction in Pattern Interrupt Status [ISR0;
addr 00B]. CERR is only applicable in T1 ESF and E1 MFAS modes. In these
modes, CERR indicates that 1 or more bit errors were found in the CRC4/CRC6
pattern block since the last time the interrupt status was read.
PDV is reported when the receive signal does not meet the pulse density
requirements of ANSI T1.403-1995 (Section 5.6). A PDV is declared whenever
more than 15 consecutive zeros or the average ones density falls below 12.5%.
RPDV is reported for the receive direction in the Alarm 1 Interrupt Status register
[ISR7; addr 004].
N8370DSE
Conexant
2-17
CONEXANT [ CONEXANT SYSTEMS, INC ]
