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BT8376KPF 参数 Datasheet PDF下载

BT8376KPF图片预览
型号: BT8376KPF
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片收发器T1 / E1和综合业务数字网( ISDN )基本速率接口 [single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces]
分类和应用: 综合业务数字网
文件页数/大小: 323 页 / 1950 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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Bt8370/8375/8376  
2.0 Circuit Description  
2.8 Transmitter  
Fully Integrated T1/E1 Framer and Line Interface  
Fs and MFAS errors are controlled by the TMERR bit in the TERROR  
register. TMERR commands a single Fs bit error in T1, or MFAS bit error in E1  
by logically inverting the next multiframe bit transmitted.  
CAS Multiframe (MAS) errors are controlled by the TSERR bit in the  
TERROR register. TSERR commands a single MAS pattern error by logically  
inverting the first MAS bit transmitted.  
2.8.7 In-Band Loopback Code Generator  
The in-band loopback code generator circuitry overwrites the transmit data with  
in-band codes of configurable value and length. These codes are sequences with  
periods of 1 to 7 bits and may, in some applications, overwrite the framing bit.  
The Transmit Inband Loopback Code Configuration register [TLB; addr 077]  
controls the functions required for this operation.  
A loopback code is generated in the transmit data stream by writing the  
loopback code to the Transmit Inband Loopback Code Pattern register [LBP; addr  
078], and then by setting the Start Inband Loopback (LBSTART) and Loopback  
Length (LB_LEN) bits in the Transmit Inband Loopback Code Configuration  
register [TLB; addr 077]. The TLB register optionally allows the loopback code  
to overwrite framing bits using the UNFRAMED bit. The LB_LEN provides  
loopback code pattern lengths of 4 to 7 bits. Patterns of 2 or 3 bits can be achieved  
by repeating the pattern in 4- or 6-bit modes, respectively. Framed or unframed all  
1s or all 0s can also be achieved by setting the pattern to all 0s or all 1s. The  
in-band loopback code generator is applicable only to T1 mode.  
2.8.8 ZCS Encoder  
The ZCS encoder encodes the single rail clock and data (unipolar) into dual rail  
data (bipolar). The Transmit Zero Code Suppression Bits (TZCS[1,0]) in the  
Transmitter Configuration register [TCR1; addr 071] selects ZCS and Pulse  
Density Violation (PDV) enforcement options for XTIP/XRING and  
TPOSO/TNEGO output pins. TZCS supports the following: Alternate Mark  
Inversion (AMI), High Density Bipolar of order 3 (HDB3), Bipolar with 8 Zero  
Suppression (B8ZS), Pulse Density Violation (PDV), Unassigned Mux Code  
(UMC), and Bipolar with 7 Zero Suppression (B7ZS).  
NOTE: ZCS encoding, which alters data content, is performed prior to the CRC  
calculation so the outgoing CRC will always be correct.  
The AMI line code requires at least 12.5% average 1s density and no more  
than 15 consecutive 0s. A 1 is encoded as either a positive or negative pulse; a 0 is  
the absence of a pulse. Two consecutive pulses of the same polarity are referred to  
as a Bipolar Violation (BPV).  
N8370DSE  
Conexant  
2-65