2.0 Functional Description
CN8330
2.1 Overview
DS3/E3 Framer with 52 Mbps HDLC Controller
Figure 2-1. Functional Block Diagram
Receive
RXPOS
RXNEG
DS3CKI
Unipolar
Conversion
LOS, LCV
VCO
MUX
DATA
CLK
RXDAT, RXCLK
TXPOS
TXNEG
TXCKI
RXBCK
RDAT[7:0]
Status: IDLE
PPDL
Receiver
FIFO
Buffer
VALFCS
SOURCELB
Rx Timing
FEAC
Channel
RXCKI
FIFEN
Receive Byte
Terminal
Data Link
Receiver
Message Buffer
Status: OOF
Frame/
Overhead
Bit Check
Receive Clock
and Data
Frame Error
Parity
Control
Interrupts
Address/Data
Path Parity
FEBE
X Bit
Microprocessor
Interface
Format
RXMSY
Frame
Recovery
Gapped Clock
CBITO,RXCCK
Control
Status
Payload
Bit Check
Status: AIS
IDLE
Transmit
TXBCK
TDAT[7:0]
SNDMSG, SNDFCS
PPDL
Transmitter
CBITI
TXCCK
TXSYO
Framing and
Overhead Bit
Insertion
FEAC
Transmit Byte
Channel
TXNRZ Data
TXDATI
TXCKI
TXSYI
Terminal Data
Link
Generator
Message Buffer
TXENCI
LINELB
FIFO Data
for Line
MUX
Loopback
Test
Payload Bit
Pattern Insert
Equipment
Feature
Select
TXPOS
TXNEG
TCLKO
Bipolar
Encoding
FEBE
Generation
MUX
RXPOS
RXNEG
DS3CKI
LINELB
2-2
Conexant
100441E
CONEXANT [ CONEXANT SYSTEMS, INC ]
