CN8330
2.0 Functional Description
DS3/E3 Framer with 52 Mbps HDLC Controller
2.3 Transmitter Operation
In E3 mode, the FAS pattern is automatically generated by the transmitter
circuitry. The transmitter also inserts the A-bit as determined from the Transmit
Alarm Control 1 bit [TxAlm1;CR00.5] and the N-bit from the terminal data link
circuitry. If ExtCBit is high, the N-bit must be provided on the CBITI pin in
response to the rising edge of TXCCK. The TXOVH/VALFCS and TXSYO
signals are active during the 12 bits of overhead. If the PPDL is enabled, the
transmitter also inserts a 1100 pattern after the normal 12-bit framing sequence
for a total of 16 overhead bits. This 16-bit pattern is for conformance with draft
standard prETS 300 214 for SMDS applications. In this mode, the
VALFCS/TXOVH and TXSYO signals are active during all 16 bits of overhead.
All overhead bits can be inserted via the serial data input by setting the ExtOvh
bit high.
Figure 2-7. C-Bit Input Timing
TXCCK
CBITI
C1 C2
C3
C1 C2
C3
C1 C2
C3
C1 C2
C3
Subframe 6
Subframe 7
Subframe 1
Subframe 2
2.3.5 Alarm Signal Generation
Three alarm signals, yellow, AIS, and idle, can be generated by the transmitter in
DS3 mode by setting the TxAlm[1,0] bit pair in the Mode Control Register.
The yellow alarm is contained in the X1 and X2 bits. The X1 and X2 bits are
normally set to 1. The yellow alarm (X1 and X2 bits = 0) can be sent by setting
the TxAlm bit pair to 01.
The AIS signal is enabled by setting the bit pair to 11. The AIS signal has
valid framing and parity, all C-bits set to zero regardless of framing mode, both
X-bits set to one, and the payload set to a 1010... pattern starting with 10 after
each overhead bit.
The idle code signal is enabled by setting the bit pair to 10. The idle code
signal has valid framing and parity, both X-bits set to one, and the payload set to a
1100... pattern starting with 11 after each overhead bit. If the framing mode is
M13, all C-bits are set to zero during transmission of the idle signal. If the
framing mode is C-bit parity, the C-bits in subframe 3 are set to zero, and the
other C-bits are from the selected source. This allows full use of the terminal data
link and transmit FEAC channel during transmission of idle code.
100441E
Conexant
2-11
CONEXANT [ CONEXANT SYSTEMS, INC ]
