CN8330
2.0 Functional Description
DS3/E3 Framer with 52 Mbps HDLC Controller
2.4 Receiver Operation
2.4.3 Received Signal Output
The received unipolar signal is recovered and provided with a clock on RXDAT
and RXCLK. An M-frame synchronization signal and gapped clock are also
provided. Figure 2-11 shows a timing diagram for DS3 mode with negligible
propagation delays for the DS3 receiver output signals. Refer to the Electrical and
Mechanical Specifications section for actual propagation delay specifications.
RXMSY is low during subframe 7 preceding the X1 bit in the first subframe.
Outputs change on the rising edge of the receive clock except for the gapped
clock on RXBCK/RXGAPCK. This clock is an inverted version of RXCLK with
a gapped pulse every 85 bits. The receive clock will be nominally 44.736 MHz.
Data on RXDAT can be clocked into the user's circuit with the rising edge of the
RXBCK/RXGAPCK if it is desired to observe only data bits (there is no rising
edge present during the overhead bit positions). The rising edge of RXBCK will
be mid-bit for each payload bit in the serial stream. An overhead indicator
RDAT[6]/RXOVH is available when the PPDL is not enabled. This signal is low
for each bit position that is an overhead bit in the receive serial stream.
Figure 2-11. Receiver Timing for Serial DS3 Mode
RXCLK
RXDAT
F4
X1
84 Info Bits
84 Info Bits
Subframe 7
Subframe 1
RXMSY
RXBCK/
RXGAPCK
RDAT[6]/
RXOVH
100441E
Conexant
2-23
CONEXANT [ CONEXANT SYSTEMS, INC ]
