3.0 Registers
CN8330
3.1 Control Registers
DS3/E3 Framer with 52 Mbps HDLC Controller
DgrCtrIE
Disagreement Counter Interrupt Enable—A control bit that allows interrupts from the DS3
Disagreement Counter [SR08;0x21]to appear on the CNTINT/LINELB output pin.
ParCtrIE
Parity Error Counter Interrupt Enable—A control bit that allows interrupts from the DS3
Parity Error Counter [SR07;0x20]to appear on the CNTINT/LINELB output pin.
0x03—Transmit FEAC Channel Byte (CR03)
7
6
5
4
3
2
1
0
TxFEAC[7]
TxFEAC[6]
TxFEAC[5]
TxFEAC[4]
TxFEAC[3]
TxFEAC[2]
TxFEAC[1]
TxFEAC[0]
TxFEAC[7:0]
Transmit FEAC Channel Message Byte—If the mode is set to C-bit parity, this register will be
used as the data byte for the transmit FEAC channel transmitter. When this byte is in the form
'0xxxxxx0' it is transmitted after every flag. If there is a one in either the most significant or
least significant bit of this register, all ones (idle) will be transmitted on the data link and
interrupts from this source will be disabled. Writing to this register clears the Transmit FEAC
Channel Interrupt bit [TxFEACItr;SR02.1] in the Data Link Interrupt Status Register
[SR02;0x12].
0x04—Feature Control Register (CR04)
The Feature Control Register is provided to enable or disable miscellaneous features in the CN8330.
7
6
5
4
3
2
1
0
TstEqSel
AMI/LCV2
DisEnc
DisLCV/Ferr
ParaEn
FEBEC[3]
FEBEC[2]
FEBEC[1]
TstEqSel
Test Equipment Feature Select—Set high to enable direct access to the B3ZS/HDB3 encoder
and to enable insertion of LCVs via the TDAT[5]/TXENCI and TDAT[4]/LCVERRI pins,
respectively. Normal operation of the transmitter is enabled when this bit is low.
AMI/LCV2
DisEnc
AMI Mode/LCV Type 2—Set high to enable AMI outputs on TXPOS and TXNEG (no
B3ZS/HDB3 encoding). If the Test Equipment Feature Select bit is also set high, then this bit
selects the type of LCV errors created when TDAT[4]/LCVERRI is active (see Table 2-1).
Disable B3ZS/HDB3 Encoding—Set high to disable the B3ZS/HDB3 encoder circuit and
provide a unipolar NRZ output instead of B3ZS/HDB3 encoded output pulses. The unipolar
output appears at the TXPOS pin and the DS3/E3 input clock is available on the TXNEG pin
(see Table 2-1).
DisLCV/Ferr
ParaEn
Disable Saturation of Line Code Violation/Frame Errors—Set to allow the LCV and Frame
Error Counters to continue counting when the maximum count has been received without
enabling the respective interrupt. This is for use with the carry output indications for these
counters as described in DS3/E3 Error Counters section in this chapter.
Parallel Data Enable—Set high to enable the PPDL transmitter and receiver as the source and sink
for data. Eight-bit data bytes on the TDAT[7:0] and RDAT[7:0] buses for the PPDL transmitter and
receiver are provided. In E3 mode, the overhead field is also altered as described in Framing-Bit
Generation under the Transmitter Operation section in the Functional Description chapter. If this
control bit is low, the TDAT[6]/TXDATI and RXDAT data lines are the data input and output,
respectively, for the DS3/E3 stream.
3-4
Conexant
100441E
CONEXANT [ CONEXANT SYSTEMS, INC ]
