CN8330
3.0 Registers
DS3/E3 Framer with 52 Mbps HDLC Controller
3.2 Status Registers
0x24—DS3 FEBE Event Counter (SR11)
7
6
5
4
3
2
1
0
DS3FEBE[7]
DS3FEBE[6]
DS3FEBE[5]
DS3FEBE[4]
DS3FEBE[3]
DS3FEBE[2]
DS3FEBE[1]
DS3FEBE[0]
DS3FEBE[7:0]
DS3 FEBE Event Counter— Increments for each M-frame where any C-bit in subframe 4
is zero.
0x25,0x26—DS3/E3 LCV Counter—Low and High Bytes (SR12,SR13)
The DS3/E3 LCV Counter is a 16-bit counter with the low byte located at address 0x25 and the high byte
located at address 0x26. If the interrupt for the DS3/E3 LCV Counter is not enabled, the counter will saturate at
65535 and the saturation indication will appear in the Counter Interrupt Status Register [SR01;0x11]. If the
interrupt is enabled, the counter will roll over and continue counting as for the 8-bit counters. In DS3 mode, this
counter increments upon each occurrence of a Bipolar Violation (BPV) and each sequence of three or more
zeroes. In E3 mode, it increments only upon each occurrence of an LCV per ITU-T O.161 (an LCV is defined
as two consecutive BPVs of the same polarity).
7
6
5
4
3
2
1
0
LCVCtr[7]
LCVCtr[6]
LCVCtr[5]
LCVCtr[4]
LCVCtr[3]
LCVCtr[2]
LCVCtr[1]
LCVCtr[0]
15
14
13
12
11
10
9
8
LCVCtr[15]
LCVCtr[14]
LCVCtr[13]
LCVCtr[12]
LCVCtr[11]
LCVCtr[10]
LCVCtr[9]
LCVCtr[8]
100441E
Conexant
3-13
CONEXANT [ CONEXANT SYSTEMS, INC ]
