Appendix A Multimegabit HDLC Formatter
CN8330
A.2 Block and Logic Diagrams
DS3/E3 Framer with 52 Mbps HDLC Controller
Figure A-2 is a logic diagram showing the functional partitioning of the pins.
This diagram pertains only to HDLC mode operation, for which some of the pins
are reassigned from CN8330 framer functions, i.e., the transmit data output
comes from a pin (RXCCK/TXNRZ) assigned to the receiver in CN8330 framer
operation.
Figure A-2. HDLC Formatter Logic Diagram
20
21
22
37
38
34-22
24
25
12
13
14
15
16
11
RXDAT
RXMSY
RXCLK
CBITO
TXNRZ
RDAT[7:0]
IDLE
VALFCS
VCO
RXBCK
RXPOS
RXNEG
DS3CKI
RXCKI
FIFEN
O Receive Serial Data Output
O No Connect
O Receive Clock Output
O No Connect
O Transmit Data Output
O Receive Byte Output
O Receive Idle Status
O Receive FCS Status
O No Connect
I
I
I
I
I
Receive Data Input
Receive Data Input
Receive Clock Input
Ground
Receiver
Section
Ground
23
O Receive Byte Clock
57
46
40
39
59
18
TXBCK
TXCCK
TXPOS
TXNEG
TXSYO
TCLKO
58
45
I
Transmit Clock Input
Ground
Transmit Byte Input
Send FCS Control
Send Message Control
TXCKI
CBITI
TDAT[7:0]
SNDFCS
SNDMSG
O Transmit Byte Clock
O No Connect
O No Connect
O No Connect
O No Connect
I
I
I
I
47–50, 53–56
Transmitter
Section
43
42
O Transmit Clock Output
67
64
65
66
2–9
ALE
CS
RD*
WR*
AD[7:0]
Address Latch Enable
Chip Select
I
I
I
I
Local Processor
Interface
Read Strobe
Write Strobe
Address-Data Bus I/O
62
63
CNTINT
DLINT
O
O
No Connect
No Connect
44
61
60
19
PPDLONLY
MON/MIC*
TESTI
VCC
Ground
Ground
I
I
I
I
Control and
Test
41
TESTO
O
No Connect
INIT*
Initialization Input
I = Input, O = Output
A-4
Conexant
100441E
CONEXANT [ CONEXANT SYSTEMS, INC ]
