2.0 Functional Description
CN8330
2.2 Line Interfaces
DS3/E3 Framer with 52 Mbps HDLC Controller
2.2.2 Receiver Line Interface
The line interface for the receive bipolar signals consists of two logic-level signals
that represent the positive and negative bipolar line pulses (RXPOS, RXNEG)
and an input (DS3CKI) for an externally derived clock at a nominal frequency of
44.736 MHz or 34.368 MHz. The receiver line signals are shown in Figure 2-3.
Nine bits of a representative input sequence are shown. The input signal is
sampled on the rising edge of the clock signal. B3ZS/HDB3 decoding is provided
internally. Decoding can be defeated for NRZ inputs by connecting the NRZ data
input to both the RXPOS and RXNEG inputs or by selecting the AMI mode/LCV
Type 2 bit [AMI/LCV2;CR04.6] in the Feature Control Register [CR04;0x04].
Figure 2-3. Clocked Receiver Input
DS3CKI
RXPOS
RXNEG
2-6
Conexant
100441E
CONEXANT [ CONEXANT SYSTEMS, INC ]
