Appendix A Multimegabit HDLC Formatter
CN8330
A.1 Introduction
DS3/E3 Framer with 52 Mbps HDLC Controller
The receiver provides complementary operation, deriving byte-organized data
and HDLC protocol status including FCS checking at serial rates up to 52 Mbps.
Figure A-1 illustrates the major data paths of the HDLC formatter.
Figure A-1. HDLC Formatter Block Diagram
Line
FCS
Loopback
Mode
Transmit Clock In
Data
Transmit Byte Clock
Transmit Data Byte
Send Message
Send FCS
8
M
U
X
HDLC
Transmit
off
Transmit Clock
Transmit Data
Receive Clock
Receive Data
on
8
Loopbacks
FCS Mode
Address/Data
Control
Microprocessor
Interface
Transmit Data
Transmit Clock
Receive Data
Receive Clock
Receive Byte Clock
Receive Data Byte
Idle Status
8
M
U
X
Clock
Data
8
on
HDLC
Receive
FCS Status
off
Source
Loopback
FCS
Mode
A-2
Conexant
100441E
CONEXANT [ CONEXANT SYSTEMS, INC ]
