CN8330
Appendix A Multimegabit HDLC Formatter
DS3/E3 Framer with 52 Mbps HDLC Controller
A.3 PPDL Transmitter
The transmit byte clock (TXBCK) is generated from the transmit clock input
(TXCKI) and has a duty cycle of 25 percent. TXBCK will nominally be
one-eighth of the TXCKI frequency but is influenced by HDLC transparency bit
insertions. In the absence of any transparency bit insertions, there will be one
pulse on TXBCK for every eight clock cycles of the TXCKI input. When a
transparency bit is inserted into the serial transmit data stream, the TXBCK
period will be lengthened to nine clock cycles of TXCKI (or 10 clock cycles if
two transparency bit insertions occur within the same octet interval). TXBCK is
present continuously even during the transmission of idle flags. The actual setup
times on TDAT[7:0], SNDMSG, and SNDFCS relative to the rising edge of
TXBCK are negative. Therefore, it is possible to read data and control from a
RAM or FIFO buffer with the rising edge. CN8330 will sample the data after the
falling edge. This allows FIFOs or RAMs with access times of 35–40 ns to be
used.
FCS calculation can be limited to the first N bytes of the transmitted message
by setting the Limit Frame Check Sequence Calculation [LimitFCS;cr05.3]
control bit. In this mode, the FCS is calculated on the first N bytes transmitted
after the opening flag and then held until the end of the message. It is then
appended to the end of the message in normal fashion. The desired number N can
be from 1 to 16 (a value of 0 gives N = 16) and is loaded in the Frame Check
Sequence Calculation Count[3:0] [FCSCnt;CR05.7:4] control field. This allows
FCS calculation only on the header information in a T1 packet voice format.
A.3.1 PPDL Receiver
The PPDL receiver circuitry is activated when the ParaEn bit in the Feature
Control Register is set. The receiver performs idle flag detection, stuffed zero
deletion, and FCS checking on the incoming data stream. The recovered data
bytes are presented on RDAT[7:0] and are valid on both the rising and falling
edges of RXBCK; the least significant bit is on RDAT[0] and the most significant
bit is on RDAT[7]; the least significant bit is the first received from the serial
input. If the payload stream contains idle flags, the IDLE pin will be high and the
flags will be present on RDAT[7:0]. If a valid FCS is received at the end of the
message block, then the VALFCS pin will be active high while IDLE is high. At
the start of the next message, both indications will go low until the end of the
incoming message has been received. If a bad FCS is received, IDLE will go high
and VALFCS will remain low. If VALFCS goes high and IDLE does not, an abort
sequence was received in the data. If there is only one flag received between
incoming packets, there will be only one RXBCK pulse present while IDLE is
high. If CRC 32-bit is low, the FCS is checked with the polynomial:
16 12
5
x +x +x +1
If a 32-bit CRC is selected by setting CRC32 bit high, then the FCS is checked
with the polynomial:
32 26 23 22 16 12 11 10
8
7
5
4
2
x +x +x +x +x +x +x +x +x +x +x +x +x +x+1
100441E
Conexant
A-7
CONEXANT [ CONEXANT SYSTEMS, INC ]
