4
4.0 Mechanical/Electrical Specifications
4.1 Timing Requirements
Table 4-1 and Figure 4-1 illustrate the timing requirements for the microprocessor
interface. The parameter t is the period of the receive DS3/E3 clock (DS3CKI).
cyc
This clock signal is used in the read circuit of the microprocessor to ensuring no
status events are missed and that counter values are accurately read.
Read operation requires the read strobe to be low for three t clock cycles
cyc
ensuring that changing status and error counts are properly processed. If a gapped
clock is applied to the circuit, it is sufficient to allow three receive clock cycles
between read strobes to allow a latching circuit to clear in the microprocessor
interface.
Table 4-1. Microprocessor Interface Timing (1 of 2)
Symbol
Parameter
Min.
Typical
Max.
Units
tas
Address Setup before ALE Low
7
—
—
ns
tcale
tah
Controller ALE Pulse Width
Address Hold after ALE Low
RD*/WR* High to ALE High
Address/Select to WR* High
Address/Select to RD* Low
34
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
trwa
tadwrh
tadrdl
10
117
17
RD* Pulse Width(1)
WR* Pulse Width
twrw (Read Operation)
3 × t
cyc
twrw (Write Operation)
100
—
3
trdd
trdh
RD* Low to Data Available
Read Data Hold Time(2)
100441E
Conexant
4-1
CONEXANT [ CONEXANT SYSTEMS, INC ]
