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CN8472A 参数 Datasheet PDF下载

CN8472A图片预览
型号: CN8472A
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道同步通信控制器( MUSYCC ™ ) [Multichannel Synchronous Communications Controller (MUSYCC?)]
分类和应用: 通信控制器
文件页数/大小: 221 页 / 2104 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CN8478/CN8474A/CN8472A/CN8471A  
5.0 Memory Organization  
Multichannel Synchronous Communications Controller (MUSYCC™)  
5.2 Descriptors  
5.2.4.2 Note for  
Interrupt Driven Drivers  
An interrupt from MUSYCC does not imply that MUSYCC read a buffer status  
descriptor and made it host-owned.  
As mentioned in Note (2) in Table 5-31, the occurrence of a MUSYCC  
interrupt and a buffer status descriptor update are not time correlated. The delay  
of the buffer status descriptor update is a maximum of 2 HDLC frames after the  
interrupt.  
The driver must read the owner field to confirm its ownership before writing a  
new buffer status descriptor. If the driver receives an interrupt and does not detect  
a host-owned buffer, it should wait a minimum of 2 HDLC frames before  
signaling an abnormal condition.  
The requirement to check the buffer status descriptor is applicable only when  
buffer status descriptor updates are enabled (INHRBSD = 0).  
5.2.4.3 Head Pointer  
The head pointer points to the first message descriptor in a list of descriptors  
assigned to a channels transmitter or receiver.  
A head pointer allows the host to specify a new list of descriptors to use for  
channel processing. This mechanism can be used after a reset to kick-start or  
reactivate channel processing which has completely processed the current list of  
descriptors.  
A head pointer also allows the host to generate a new list of descriptors in  
memory before performing a list transition; that is, while MUSYCC processes  
data in one list, the host can process data in a separate list, and, when appropriate,  
can switch the lists.  
Table 5-20 lists the head pointers and their descriptions.  
Table 5-20. Head Pointer  
Bit  
Name  
Field  
Value  
Description  
31:2  
HEADPTR[29:0]  
These 30 bits are appended with 00b to form a dword-aligned 32-bit address. This  
address points to the first Message Descriptor in a list of descriptors.  
1:0  
HEADPTR[1:0]  
0
Ensures dword alignment.  
5.2.4.4 Message Pointer  
The message pointer points to the current message descriptor being serviced. This  
pointer is maintained in a fixed memory location relative to a Group Base Pointer  
in shared memory.  
Table 5-21 lists the message pointers and their descriptions.  
Table 5-21. Message Pointer  
Bit  
Name  
Field  
Value  
Description  
31:2  
MSGPTR[29:0]  
These 30 bits are appended with 00b to form a dword-aligned 32-bit address. This  
word pointer points to the first dword of a Message Descriptor.  
1:0  
MSGPTR[1:0]  
0
Ensures dword alignment.  
100660E  
Conexant  
5-31