CN8478/CN8474A/CN8472A/CN8471A
1.0 System Description
Multichannel Synchronous Communications Controller (MUSYCC™)
1.1 Pin Descriptions
Figure 1-12. CN8478 Logic Diagram
198
197
196
195
194
193
192
190
(1)
Bus Grant Acknowledge I/O
Hold Acknowledge
Hold Request O
Expansion Bus Interrupt
BGACK*
ECLK
EBE[3:0]*
EAD[31:0]
O
O
Clock
I
HLDA (BG*)
HOLD (BR*)
EINT*
ALE* (AS*)
RD* (DS*)
WR* (R/WR*)
Expansion Bus Byte Enable
(2)
I/O Expansion Bus Address/Data
Expansion Bus
Interface
I
Address Latch Enable O
Read Strobe
O
Write Strobe/Read O
Serial Interface
207
Out-Of-Frame
Clock
Synchronization
Data
Out-Of-Frame
Clock
Synchronization
I
I
I
I
I
I
I
I
I
ROOF[7]
RCLK[7]
RSYNC[7]
RDAT[7]
ROOF[6]
RCLK[6]
RSYNC[6]
RDAT[6]
ROOF[5]
140
149
138
TCLK[7]
TSYNC[7]
TDAT[7]
I
I
O
Clock
Synchronization
Data
208
1
2
7
8
9
10
17
Receive Serial
Transmit Serial
Channel Group Channel Group
7
7
131
130
129
TCLK[6]
TSYNC[6]
TDAT[6]
I
I
O
Clock
Synchronization
Data
Receive Serial Transmit Serial
Channel Group Channel Group
6
6
Data
Out-Of-Frame
125
124
123
TCLK[5]
TSYNC[5]
TDAT[5]
I
I
O
Clock
Synchronization
Data
18
19
20
25
26
29
30
3
4
5
6
11
12
15
16
21
22
23
24
31
32
33
34
35
36
37
38
Receive Serial Transmit Serial
Channel Group Channel Group
Clock
Synchronization
Data
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
RCLK[5]
RSYNC[5]
RDAT5]
ROOF[4]
RCLK[4]
RSYNC[4]
RDAT[4]
ROOF[3]
RCLK[3]
RSYNC[3]
RDAT[3]
ROOF[2]
RCLK[2]
RSYNC[2]
RDAT[2]
ROOF[1]
5
5
Out-Of-Frame
117
116
115
TCLK[4]
TSYNC[4]
TDAT[4]
I
I
O
Clock
Synchronization
Data
Receive Serial Transmit Serial
Channel Group Channel Group
Clock
Synchronization
Data
Out-Of-Frame
Clock
Synchronization
Data
Out-Of-Frame
Clock
Synchronization
Data
Out-Of-Frame
Clock
Synchronization
Data
Out-Of-Frame
Clock
Synchronization
Data
JTAG Clock
JTAG Reset
JTAG Mode Select
4
4
143
142
141
TCLK[3]
TSYNC[3]
TDAT[3]
I
I
O
Clock
Synchronization
Data
Receive Serial Transmit Serial
Channel Group Channel Group
3
3
136
135
134
TCLK[2]
TSYNC[2]
TDAT[2]
I
I
O
Clock
Synchronization
Data
Receive Serial Transmit Serial
Channel Group Channel Group
2
2
128
127
126
TCLK[1]
TSYNC[1]
TDAT[1]
I
I
O
Clock
Synchronization
Data
Receive Serial Transmit Serial
Channel Group Channel Group
RCLK[1]
RSYNC[1]
1
1
I
I
RDAT[1]
ROOF[0]
RCLK[0]
RSYNC[0]
RDAT[0]
TCK
TRST*
TMS
TDO
122
121
120
TCLK[0]
TSYNC[0]
TDAT[0]
I
I
O
Clock
Synchronization
Data
Receive Serial Transmit Serial
Channel Group Channel Group
I
I
I
I
I
I
0
0
114
113
112
TM[0]
TM[1]
TM[2]
I
I
I
Scan Enable
Scan Mode Bit 1
Scan Mode Bit 2
Boundary Scan
Test Signal
Scan Chain
Test Access
JTAG Data Out O
39
JTAG Data In
I
TDI
43
45
46
60
75
76
79
80
83
84
40
41
(4)
Clock
Reset
Grant
I
I
I
I
PCLK
PRST*
GNT*
INTB*
INTA*
CBE[3:0]*
REQ*
O
O
O
O
O
PCI Interrupt B
PCI Interrupt A
Command and Byte Enables
Request
47
85
Initialization Device Select
IDSEL
FRAME*
IRDY*
TRDY*
DEVSEL*
STOP*
PERR*
PAR
Frame I/O
Initiator Ready I/O
Target Ready I/O
Device Select I/O
Stop I/O
SERR*
System Error
Host (PCI)
Interface
Parity Error I/O
Parity I/O
Address and Data Bus I/O
86
(3)
AD[31:0]
98
M66EN
I
M66EN
8478_004
NOTE(S):
(1)
(2)
(3)
(4)
(5)
EBE [3:0]* pin numbers are 199-200, 203-204.
EAD [31:0] pin numbers are 144-146, 149-152, 145-155, 158-163, 166-170, 173-174, 176-180, 183-184, 187-189.
AD [31:0] pin numbers are 48-51, 54, 56-58, 61-62, 65-66, 69-72, 88, 90-94, 97, 99, 101-103, 105-109.
CBS [3.0]* pin numbers are 59, 74, 87,100.
An active low signal is denoted by a trailing asterisk (*).
100660E
Conexant
1-17
CONEXANT [ CONEXANT SYSTEMS, INC ]
