4.0 Serial Interface
CN8478/CN8474A/CN8472A/CN8471A
4.7 Tx and Rx FIFO Buffer Allocation and Management
Multichannel Synchronous Communications Controller
Figure 4-7. Transmit Data Flow
Control
1/2 FIFO
Transmit
Channel
Shared
Memory
BLP
DMAC
Data
Data
PCI
Bus
1/2 FIFO
Internal Data Buffer
8478_019
NOTE(S): 1/2 FIFO = BUFFLEN+1
The allocation of internal data buffers requires an understanding of how the
total available FIFO buffer space depends on whether subchannels are enabled
within that channel group. Table 4-2 specifies 64 dwords of internal data buffer
are available to allocate as FIFO buffer space among the 32 channels of each
channel group when any channel within that group is configured to operate as a
subchannel (SUBDSBL = 0 in the Group Configuration Descriptor). Table 4-2
further specifies that an additional 64 dwords of internal data buffer (128 dwords
total) are available to allocate as FIFO buffer space among the channel group by
reusing the subchannel map area when all subchanneling within that group is
disabled (SUBDSBL = 1).
Other important considerations for allocating internal data buffers include the
number of active channels per group, the channels’ data rate, and the channels’
PCI latency tolerance. Examples given later in this section describe scenarios
where all available internal data buffer space is evenly distributed to form equal
length FIFO buffers for each channel in the group, presuming each channel
operates at the same data rate, and there are a variable number of channels per
group. However, internal data buffer allocation is flexible and allows the host to
assign larger FIFO buffers to channels operating at higher data rates. For
applications operating high speed channels (i.e., hyperchannels), the host
typically allocates 2 dwords (64 bits) of internal data buffer for each 64 kbps
increment in the channel’s data rate. For example, a 1920 kbps hyperchannel
consisting of 30 time slots would typically be allocated 60 dwords of FIFO buffer
space. Smaller FIFO buffers can be allocated if there are multiple, high-speed
channels configured within one group, but at the expense of some PCI latency
tolerance.
PCI latency tolerance equals the maximum length of time a particular channel
can operate normally between PCI bus transactions without reaching an internal
buffer overflow or underflow condition. Therefore, PCI latency tolerance is
primarily dependent on each channel’s FIFO buffer size. Because of MUSYCC’s
internal data buffer scheme, each transmit channel’s PCI latency tolerance is
expressed as the amount of time required to send data from half the FIFO buffer
size [(i.e., (BUFFLEN + 1) dwords)]. While a receive channel’s PCI latency
tolerance is expressed as 1/2 FIFO buffer size plus 1 additional dword
[i.e., (BUFFLEN + 2) dwords]. A 64 kbps channel that is allocated 4 dword
transmit and receive FIFO buffers can tolerate up to 2 dwords (1 ms) of bus
latency in the transmit direction and 3 dwords (1.5 ms) of bus latency in the
receive direction.
4-12
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
