5.0 Memory Organization
CN8478/CN8474A/CN8472A/CN8471A
5.2 Descriptors
Multichannel Synchronous Communications Controller (MUSYCC™)
5.2.1.2 Dual Address
Cycle Base Pointer
MUSYCC supports 32-bit and 64-bit memory addressing. The Dual Address
Cycle Base Pointer (DACBASE) supports 64-bit memory addressing and is
described in Table 5-7.
If the value of DACBASE is 0, MUSYCC initiates all memory access cycles
without dual-addressing. If the value is non-0, MUSYCC initiates all memory
access cycles with dual-addressing.
For cycles without dual-addressing, MUSYCC uses the AD[31:0] signal lines
to indicate the address of the memory access. During the address phase,
MUSYCC encodes the type of access cycle (e.g., read, write,...) in the
Command/Byte Enable signal lines, CBE[3:0]*. The address phase lasts one
PCLK period.
For cycles with dual-addressing, MUSYCC multiplexes a 64-bit address onto
the AD[31:0] signal lines and adds an additional PCLK period to the address
phase. To indicate 64-bit addressing, MUSYCC encodes the dual address code
onto the CBE[3:0]* signal lines during the first PCLK period of the address
phase. MUSYCC encodes the access type code (e.g., read, write) onto the
CBE[3:0]* signal lines during the second PCLK period of the address phase.
When MUSYCC accesses a 64-bit memory address using dual addressing, the
upper 32 bits of the address are fixed to a non-0 value from DACBASE. To
change from 64-bit addressing to 32-bit addressing, the value of DACBASE must
be zeroed. Although MUSYCC is capable of initiating 64-bit addressing when in
master mode, it responds only to 32-bit access cycles without dual-addressing.
Table 5-7. Dual Address Cycle Base Pointer
Bit
Field
Name
Value
Description
31:0
DACBASE[31:0]
—
Dual Address Cycle Base Pointer. A 32-bit base register when non-0 causes all
MUSYCC master operations (read/write) to use PCI Dual Address Cycle. The value
in this register would be the upper 32-bits of the 64-bit addressing.
5.2.2 Channel Group Level Descriptors
Channel Group Descriptors contain all information needed to configure one
channel group and the associated 32 logical channels, while maintaining pointers
to buffer descriptors for each channel and direction. The contents of the Channel
Group Descriptor are listed in Table 5-2, Group Structure Memory Map.
5.2.2.1 Group Base
Pointer
The Group Base Pointer (GBASE) register per channel group within the host
interface contains a 2 kB pointer aligned to a corresponding Channel Group
Descriptor in shared memory, as described in Table 5-8.
Table 5-8. Group Base Pointer
Bit
Name
Field
Value
Description
31:11
GBASEx[20:0]
—
These 21 bits are appended with 11 0s to form a 2 k block-aligned 32-bit address
pointing to the first dword of the channel group structure for Channel Group x.
10:0
GBASEx[10:0]
0
These 11 bits appended to GBASE ensure 2 kB block alignment.
5-12
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
