4.0 Serial Interface
CN8478/CN8474A/CN8472A/CN8471A
4.7 Tx and Rx FIFO Buffer Allocation and Management
Multichannel Synchronous Communications Controller
4.7.3.1 Transmit Data
Bit Output Value
Determination
The TDAT signal from MUSYCC is the only output signal in the serial interface.
For each bit time specified by the TCLK input signal to MUSYCC and on each
active edge for a data bit specified by the TDAT_EDGE bit field, a value for the
TDAT bit must be determined and output (Table 5-12, Port Configuration
Descriptor). Figure 4-8 illustrates the logic used to determine the output value.
Figure 4-8. Transmit Data Bit Output Value Determination
if ( TRANSMITTER_NOT_ENABLED )(1)
TDAT <= three-state
else
if ( CHANNEL_IS_MAPPED )(2)
if ( CHANNEL_IS_ACTIVATED )(3)
TDAT = BLP_OUTPUT(4)
else
TDAT = `logic 1'
else
if ( THREE_STATE_OUTPUT )(5)
TDAT = three-state
else
TDAT = `logic 1'
8478_020
NOTE(S):
(1)
TRANSMITTER_NOT_ENABLED. (Check TXENBL bit field in Table 5-10, Group Configuration Descriptor.)
CHANNEL_IS_MAPPED. (Verify channel to time slot mapping enabled in Table 5-14, Transmit or Receive Time Slot Map.)
CHANNEL_IS_ACTIVATED. Verify Channel Activate Service Request issued.
BLP_OUTUT. Data taken from shared memory, through the internal FIFO and ready for transmission.
THREE_STATE_OUTPUT. Check TRITX bit field in Port Configuration Descriptor.
(2)
(3)
(4)
(5)
4-16
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
