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2.0 Host Interface
Multichannel Synchronous Communications Controller (MUSYCC™)
2.2 PCI Configuration Registers
The predictable worst case time MUSYCC must wait for the bus in a system
with k masters with equal latency timers is [k x (T + 8)].
If one MUSYCC is configured with all 256 channels active, and receiving and
transmitting at 64 kbps, it must maintain a data rate of 16 Mbps across the PCI
bus. Therefore:
•
256 channels x (64 kbps Rx + 64 kbps Tx) = 32,768 kbps
With 32 bits in each dword, the data rate in kilo dwords per second (kdwps) is:
32,768 kbps / (32 bits/dword) = 1,024 kdwps
•
The 16-clock rule (PCI Local Bus Specification, Revision 2.1) requires that a
single access device must complete the access cycle within 16 clock cycles of the
FRAME* signal being asserted. For devices capable of burst-mode, the 16-clock
rule applies to the completion of the first data cycle.
2.2.6.2 Latency
Computation—Single
Dword Access
Assuming the worst case scenario where the system allows only single dword
access, even a burst-mode device such as MUSYCC must relinquish the PCI bus
within 16 clock cycles from receiving the bus. Using this scenario, the
calculations continue as follows:
•
•
•
•
The time per dword would be:
1 dword / 1,024 kdwps = 0.98 µs per dword
Assuming a PCI bus rate of 33 MHz, the time per clock cycle would be:
1 cycle / 33 MHz = 30.303 ns per clock cycle
Assuming a PCI bus rate of 66 MHz, the time per clock cycle would be:
1 cycle / 66 MHz = 15.152 ns per clock cycle
To get the number of clock cycles per dword:
0.98 µs per dword / 0.0303 µs per clock cycle = 33 PCI clock cycles per
dword
•
To get the number of clock cycles per dword:
0.98 µs per dword / 0.0152 µs per clock cycle = 66 PCI clock cycles per
dword
With one MUSYCC and one host, the host can use the following:
•
Assuming a PCI bus rate of 33 MHz:
33 cycles per dword – 16 cycles (16 clock rule) = 17 clock cycles between
dword transfers
•
Assuming a PCI bus rate of 66 MHz:
66 cycles per dword – 16 cycles (16 clock rule) = 50 clock cycles between
dword transfers
Accordingly, MUSYCC's T must be:
•
Assuming a PCI bus rate of 33 MHz:
17 cycles – 8 cycle (target latency) = 9 clock cycles. As T has a granularity
of 8 units, T must be programmed to 8 PCI clock cycles.
Assuming a PCI bus rate of 66 MHz:
•
50 cycles – 8 cycle (target latency) = 42 clock cycles. As T has a
granularity of 8 units, T must be programmed to 40 PCI clock cycles.
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