CX11656-11 参数 Datasheet PDF下载

CX11656 HomePlug 1.0 PHY Data Sheet

Figures

Figure 1-1. CX11656 HomePlug 1.0 PHY Simplified Hardware Interface..........................................................................1-1

Figure 1-2. CX11656 HomePlug 1.0 PHY Functional Block Diagram................................................................................1-2

Figure 2-1. CX11656 PHY Hardware Interface Signals - 144-Pin LQFP ............................................................................2-2

Figure 2-2. CX11656 PHY Pin Signals - 144-Pin LQFP ....................................................................................................2-3

Figure 3-1. CX11656 PHY Block Diagram ........................................................................................................................3-1

Figure 3-2. MII Data Interface with MDI Control ..............................................................................................................3-2

Figure 3-3. MII TX Waveform ..........................................................................................................................................3-3

Figure 3-4. MII RX Waveform..........................................................................................................................................3-4

Figure 3-5. MII TX with Collision Based on RX Activity ....................................................................................................3-4

Figure 3-6. MII Receive Timing........................................................................................................................................3-5

Figure 3-7. MII Transmit Timing......................................................................................................................................3-5

Figure 3-8. MII Flow Control Overview, Part 1 .................................................................................................................3-7

Figure 3-9. MII Flow Control Overview, Part 2 .................................................................................................................3-7

Figure 3-10. Partition of Serial Bit Stream to Nibble Stream ............................................................................................3-8

Figure 3-11. MDI Receive Timing ....................................................................................................................................3-9

Figure 3-12. MDI Transmit Timing...................................................................................................................................3-9

Figure 3-13. MDI Frame Structure .................................................................................................................................3-10

Figure 3-14. GPSI Data Interface with SPI Control.........................................................................................................3-12

Figure 3-15. GPSI Flow Control .....................................................................................................................................3-13

Figure 3-16. GPSI Transmit Timing ...............................................................................................................................3-13

Figure 3-17. GPSI Receive Timing .................................................................................................................................3-13

Figure 3-18. SPI Slave Port Timing................................................................................................................................3-16

Figure 3-19. AFE TX and RX Activity ..............................................................................................................................3-17

Figure 3-20. AFE Clock Waveforms................................................................................................................................3-17

Figure 3-21. AFE Transmit Timing Diagram ...................................................................................................................3-18

Figure 3-22. AFE Receive Timing Diagram .....................................................................................................................3-18

Figure 3-23. SPI Master Interface Signal Timing Diagram .............................................................................................3-21

Figure 4-1. Package Dimensions - 144-Pin LQFP.............................................................................................................4-1

Figure 5-1. Ethernet Router Application Block Diagram ...................................................................................................5-1

Figure 5-2. USB Application Block Diagram .....................................................................................................................5-2

Figure 5-3. Embedded Application Block Diagram ...........................................................................................................5-3

102069A

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