CX25870/871
1.0 Functional Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3 Device Description
1.3.45 VGA(RGB)—DAC Output Operation
In this mode of operation, the CX25870/871 acts as a general-purpose triple
high-speed D/A converter used to drive video receivers, such as PC monitors. The
encoder accomplishes this by bypassing most of the encoder blocks utilized for
television outputs, such as the Flicker Filter and FIFO and routing the RGB or
YCrCb digital data straight through to the on-chip 10-bit DACs. Once the data
arrives at the DACs, it is quickly converted to a set of 700 mV peak-to-peak
analog outputs, streamed through the respective DAC_X output pins, and routed
onto the rest of the graphics system according to the PCB layout.
Optimal performance is achieved when the CX25870/871’s current controlled
DACs are terminated into appropriate resistive loads to produce voltage outputs.
The chip’s DAC outputs are specifically designed to produce video output levels
with a total peak-peak active-region amplitude of 700 mV when directly
connected to a single-ended, doubly terminated (Req = 37.5 Ω) load. With the
recommended loading of two 75 Ω 1 percent resistors (one each for the
transmitting and receiving side), the full-scale video amplitude is from 286 mV
(blanking) to 986 mV (maximum luminance) and synchronization pulses from
0 mV (negative sync tip) to 286 mV (blanking) respectively. The analog
synchronization pulse is generated by the CX25870/871 every time it receives a
falling edge on either the HSYNC* or the VSYNC* input by default. These sync
pulses can be disabled for the RGB outputs by following the steps found in
Table 1-30.
On power-up, the CX25870/871 will output NTSC or PAL standard-definition
television outputs depending on the state of the PAL pin. To switch the device into
VGA-DAC Output Mode with bilevel syncs embedded on every Red/Green/Blue
(RGB) analog output, perform the sequence of serial writes found in Table 1-29
only.
Table 1-29. Serial Writes Required to Switch CX25870/871 into VGA/DAC Output Operation
Bit Name
SLAVER
Location
Value
Comment
Bit 5–Register 0xBA
Bit 7–Register 0xA0
Bit 1–Register 0xA2
Ensures CX25871 in slave or pseudo-master interface
CLKI used as pixel clock source.
1
1
0
EN_XCLK
SETUP
Setup off. The +56 mV pedestal setup is disabled for active
video lines.
OUT_MODE[1:0]
Bits 3:2–Register D6
Video [0-3] = 11 = VGA Output Mode:
DAC_A = Video[0] = Red
11
DAC_B = Video[1] = Green
DAC_C = Video[2] = Blue
DAC_DISD
Bit 3–Register 0xBA
Disables DACD output. Current is set to 0 mA. Output
voltage goes to 0 V.
1
100381B
Conexant
1-85
CONEXANT [ CONEXANT SYSTEMS, INC ]
