1.0 Functional Description
CX25870/871
1.3 Device Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3.23 Analog Vertical Sync
The analog vertical sync duration is selectable as either 2.5 or 3 lines by register
bit VSYNC_DUR. If VSYNC_DUR = 1, 3 lines are selected; if
VSYNC_DUR = 0, 2.5 lines are selected.
The device automatically blanks the video from the start of the horizontal sync
interval through the end of the burst, as well as the vertical sync to prevent
erroneous video timing generation.
1.3.24 Analog Video Blanking
Analog video blanking is controlled by the H_BLANKO, V_BLANKO, and
V_ACTIVEO registers. Together they define an active region where pixels are
displayed. V_BLANKO defines the number of lines from the leading edge of the
analog vertical sync to the first active output line per field. V_ACTIVEO defines
the number of active output lines. H_BLANKO defines the number of output
pixels from the leading edge of horizontal sync to the first active output pixel.
H_ACTIVE defines the number of active output pixels.
The device automatically blanks video from the start of the horizontal sync
interval through the end of the burst, as well as the vertical sync interval to
prevent erroneous video timing generation.
1.3.25 Video Output Standards Supported
There are several bits (625LINE, SETUP, VSYNC_DUR, PAL_MD, FM,
DIS_SCRST), a PAL pin, and various autoconfiguration modes, that control the
generation of various video standards. (These are summarized in Table 1-18.)
They allow the generation of all the different NTSC, PAL, and SECAM video
standards. The aforementioned bits control the specific encoding process
parameters. It is likely other registers may need to be modified to meet all the
video parameters of the particular video standard. Video timing diagrams are
illustrated in Figures 1-11 through 1-22. These show typical events that occur for
each type of video format.
1-42
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
