2.0 Circuit Description
CX28394/28395/28398
2.5 Microprocessor Interface
Quad/x16/Octal—T1/E1/J1 Framers
2.5.1 Address/Data Bus
In Non-Multiplexed Address Mode, A[11:0] (A[10:0] for CX28394) provides the
address for the register access. In Multiplexed Address Mode, A[11:8] (A[10:8]
for CX28394) and AD[7:0] provide the address. In both modes, the data bytes
flow over the shared bidirectional, byte-wide bus, AD[7:0].
2.5.2 Bus Control Signals
Four signals control operation of the interface port. The control signals are
AS*/ALE, CS*, DS*/RD*, and R/W*(WR*). An additional pin, MOTO*, selects
whether the interface signals are of a Motorola or Intel style.
When MOTO* is low, indicating a Motorola-style interface, CS*, AS*, R/W*,
and DS* signals are expected. When MOTO* is high, indicating an Intel-style
interface, CS*, ALE, RD*, and WR* signals are expected.
When MOTO* is high, the address lines are multiplexed with the data. This
pin should usually be tied high for Intel devices and tied low for Motorola
devices. SYNCMD puts the interface into the Synchronous Processor Interface
Mode. Motorola 68000 processors typically have SYNCMD tied high if MCLK is
connected to the MPU clock source; Intel 8051 processors have SYNCMD tied
low (see Table 2-7).
Table 2-7. Microprocessor Interface Operating Modes
MOTO*
SYNCMD
Description
0
0
1
1
0
1
0
1
Asynchronous Motorola, internal clock
Synchronous Motorola, external clock
Asynchronous Intel, internal clock
Synchronous Intel, external clock
2.5.3 Interrupt Requests
Figure 2-28, Interrupt Generation Block Diagram, details the interrupt generation
process. The INTR* output pin is an active low, open-drain type output which
provides a common interrupt request for all eight framers and the LIU serial
interface.
Each framer includes interrupt status registers (ISR[7:0]), interrupt enable
registers (IER[7:0]), and an interrupt request register (IRR). Events such as alarm
status changes and sync signals are latched in ISR registers until read by the
microprocessor. Each ISR bit has a corresponding IER bit used to enable or
disable interrupt generation. If enabled, an ISR event is reported in the
appropriate IRR bit.
2-56
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
