2.0 Circuit Description
CX28394/28395/28398
2.8 Joint Test Access Group
Quad/x16/Octal—T1/E1/J1 Framers
2.8 Joint Test Access Group
The device incorporates printed circuit board testability circuits in compliance
with IEEE Std. P1149.1a–1993, IEEE Standard Test Access Port and
Boundary–Scan Architecture, commonly known as JTAG (Joint Test Action
Group).
The JTAG includes a Test Access Port (TAP) and several data registers. The
TAP provides a standard interface through which instructions and test data are
communicated (see Figure 2-30). A Boundary Scan Description Language
(BSDL) file is available from Conexant upon request.
The test access port consists of TDI, TCK, TMS, TDO and TRST* pins.
Figure 2-30. Test Access Port (TAP) Diagram
TCK
TMS
JTAG Port
TRST*
TDO1
TDO2
TDI
(CX28395)
(CX28394, CX28398) TDO
100054_003
2.8.1 Instructions
In addition to the required BYPASS, SAMPLE/PRELOAD, and EXTEST
instructions, IDCODE instruction is supported. There is also one private
instruction. Table 2-8 lists the JTAG instructions along with their codes.
Table 2-8. JTAG Instructions
Instruction
Code
BYPASS
SAMPLE/PRELOAD
EXTEST
111
001
000
010
xxx
IDCODE
Private
2-62
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
