2.0 Circuit Description
CX28394/28395/28398
2.2 Receiver
Quad/x16/Octal—T1/E1/J1 Framers
2.2.10 Receive Data Link
The RCVR contains two independent data link controllers (DL1 and DL2) and a
Bit-Oriented Protocol (BOP) transceiver. DL1 and DL2 can be programmed to
send and receive HDLC formatted messages in the Message-Oriented Protocol
(MOP) mode. Alternatively, unformatted serial data can be sent and received over
any combination of bits within a selected time slot or F-bit channel. The BOP
transceiver can preemptively receive and transmit BOP messages, such as ESF
Yellow Alarm.
2.2.10.1 Data Link
Controllers
DL1 and DL2 control two serial data channels operating at multiples of 4 kbps up
to the full 64 kbps time slot rate by selecting a combination of bits from odd,
even, or all frames. Both DL1 and DL2 support ESF Facilities Data Link (FDL),
SLC-96 Data Link, Sa Data Link, Common Channel Signaling (CCS), Signaling
System #7 (SS7), ISDN LAPD channels, Digital Multiplexed Interface (DMI)
Signaling in TS24, as well as the latest ETSI V.51 and V.52 signaling channels.
DL1 and DL2 each contain a 64-byte receive FIFO buffer.
Both data link controllers are configured identically, except for their offset in
the register map. The DL1 address range is 0A4 to 0AE, and the DL2 address
range is 0AF to 0B9. From this point on, DL1 is used to describe the operation of
both data link controllers.
DL1 is enabled using the DL1 Control register [DL1_CTL; addr 0A6]. DL1
will not function until it is enabled. DL1_CTL also controls the format of the
data. The following data formats [DL1[1:0]; addr 0A6] are supported on the data
link: Frame Check Sequence (FCS), non-FCS, Pack8, or Pack6. FCS and
non-FCS are HDLC formatted messages. Pack8 and Pack6 are unformatted
messages with 8 bits per FIFO access, or 6 bits per FIFO access, respectively (see
Table 2-3).
Table 2-3. Commonly Used Data Link Settings
Data Link
Frame
Time Slot
Time Slot Bits
Mode
ESF FDL
T1DM R Bit
SLC-96
Odd
All
0 (F-bits)
Don’t Care
00000010
Don’t Care
11111111
00001000
FCS
FCS
24
Even
All
0 (F-bits)
Pack6
FCS
ISDN LAPD
Sa4
N
1
Odd
FCS
NOTE(S): N represents any T1/E1 time slot.
The time slot and bit selection are performed through the DL1 Time Slot
Enable register [DL1_TS; addr 0A4] and the DL1 Bit Enable register [DL1_BIT;
addr 0A5]. The DL1 Time Slot Enable register selects the frames and time slot to
extract the data link. The frame select tells the receiver to extract the time slot in
all frames, odd frames, or even frames. The time slot enable is a value between 0
and 31 that selects which time slot to extract. The DL1 Bit Enable register selects
which bits will be extracted in the selected time slot. Refer to Table 2-3 for the
common frame, time slot, time slot bits, and modes used.
2-16
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
