CX82100-51 参数 Datasheet PDF下载

CX82100 Home Network Processor Data Sheet

2

CX82100 HNP Hardware Interface ....................................................................................................... 2-1

2.1

CX82100 HNP Hardware Interface Signals ..................................................................................................................2-1

2.1.1

CX82100-11/-12/-51/-52 Signal Interface and Pin Assignments ..................................................................2-1

2.1.2

CX82100-41/-42 Signal Interface and Pin Assignments...............................................................................2-1

2.1.3

CX82100 HNP Signal Definitions .................................................................................................................2-1

CX82100 HNP Electrical and Environmental Specifications........................................................................................2-17

2.2.1

DC Electrical Characteristics ......................................................................................................................2-17

2.2.2

Operating Conditions, Absolute Maximum Ratings, and Power Consumption............................................2-18

Optional GPIO and Host Signal Usage .......................................................................................................................2-19

Interface Timing and Waveforms...............................................................................................................................2-21

2.4.1

External Memory Interface (SDRAM).........................................................................................................2-21

2.4.2

Host Interface Timing ................................................................................................................................2-21

2.4.3

EMAC Interface Timing ..............................................................................................................................2-21

2.4.4

USB Interface Timing.................................................................................................................................2-21

2.4.5

GPIO Interface Timing ...............................................................................................................................2-21

2.4.6

Interrupt Timing ........................................................................................................................................2-22

2.4.7

Clock Reset Timing....................................................................................................................................2-22

2.4.8

Reset Timing .............................................................................................................................................2-22

Package Dimensions .................................................................................................................................................2-23

HNP Memory Map.......................................................................................................................................................3-1

Starting Addresses ......................................................................................................................................................3-3

3.2.1

ARM Vector Table........................................................................................................................................3-3

Endianness..................................................................................................................................................................3-4

Boot Procedure ...........................................................................................................................................................3-4

DMA Channel Definition ..............................................................................................................................................4-1

DMA Requests and Data Transfer................................................................................................................................4-1

Control Registers ........................................................................................................................................................4-2

DMAC Register Memory Map ......................................................................................................................................4-3

Control Register Formats.............................................................................................................................................4-4

4.5.1

DMAC x Current Pointer 1 (DMAC_{x}_Ptr1) ...............................................................................................4-4

4.5.2

DMAC x Indirect/Return Pointer 1 (DMAC_{x}_Ptr2)....................................................................................4-4

4.5.3

DMAC x Buffer Size Counter 1 (DMAC_{x}_Cnt1).........................................................................................4-4

4.5.4

DMAC x Buffer Size Counter 2 (DMAC_{x}_Cnt2).........................................................................................4-4

4.5.5

DMAC x Buffer Size Counter 3 (DMAC_{x}_Cnt3).........................................................................................4-5

Three Basic Modes of Address Generation ..................................................................................................................4-6

4.6.1

Source or Destination Mode ........................................................................................................................4-6

4.6.2

Circular Buffer Modes..................................................................................................................................4-6

Direct Circular Buffer ...........................................................................................................................4-6

4.6.3

Indirect Circular Pointer Table..............................................................................................................4-7

Linked List Mode .........................................................................................................................................4-9

Embedded Tail Linked List Descriptor Mode ........................................................................................4-9

Indirect/Table Linked List Descriptor Mode........................................................................................4-12

2.2

2.3

2.4

2.5

3

HNP Memory Architecture ................................................................................................................... 3-1

3.1

3.2

3.3

3.4

4

DMAC Interface Description................................................................................................................. 4-1

4.1

4.2

4.3

4.4

4.5

4.6

iv

Conexant Proprietary and Confidential Information

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