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external amplifier is recommended if driving non-amplified
speakers.
A digital speaker output (SPKMD) is provided which
reflects the received analog input signal digitized to TTL
high or low level by an internal comparator to create a PC
Card (PCMCIA)-compatible signal.
Additional Information
Additional information is provided in the RP56LD,
RP336LD, and RP144LD Modem Designer's Guide (Order
No. 1155).
indicate the corresponding FIFO buffer half full (8 or more
bytes loaded) status. TXFNF and RXFNE bits indicate the
TXFIFO buffer not full and RXFIFO buffer not empty
status, respectively. An interrupt mask register allows an
interrupt request to be generated whenever the TXFNF,
RXFNE, RXHF, or TXHF status bit changes state. The
128-byte FIFO extensions are enabled by default and can
be disabled by clearing a bit in RAM.
DMA Support Interrupt Request Lines
DMA support is available in synchronous, asynchronous,
and HDLC parallel data modes. Control bit DMAE enables
and disables DMA support. When DMA support is
enabled, the MDP ~RI and ~DSR lines are assigned to
Transmitter Request (TXRQ) and Receiver Request
(RXRQ) hardware output interrupt request lines,
respectively. The TXRQ and RXRQ signals follow the
assertion of the TDBE and RDBF interrupt bits thus
allowing the DTE/host to respond immediately to the
interrupt request without masking out status bits to
determine the interrupt source.
NRZI Encoding/Decoding
NRZI data encoding/decoding may be selected in
synchronous and HDLC modes instead of the default NRZ
(control bit NRZIEN). In NRZ encoding, a 1 is represented
by a high level and a 0 is represented by a low level. In
NRZI encoding, a 1 is represented by no change in level
and a 0 is represented by a change in level.
ITU-T CRC-32 Support
ITU-T CRC-32 generation/checking may be selected
instead of the default ITU-T CRC-16 in HDLC mode using
DSP RAM access.
Caller ID Demodulation
Caller ID information can be demodulated in V.23 1200
receive configuration and presented to the host/DTE in
serial (RXD) and parallel (RBUFFER) form.
Telephone Line Interface
Line Transformer Interface.
V.90/K56flex/V.34/V.32
bis/V.32 places high requirements upon the Data Access
Arrangement (DAA) to the telephone line. Any non-linear
distortion generated by the DAA in the transmit direction
cannot be canceled by the MDP's echo canceller and
interferes with data reception. The designer must,
therefore, ensure that the total harmonic distortion seen at
the RXA input to the MDP be at least 65 dB below the
minimum level of received signal. Due to the wider
bandwidth requirements in V.90, K56flex, and V.34, the
DAA must maintain linearity from 10 Hz to 4000 Hz.
Relay Control.
Direct control of the off-hook and talk/data
relays is provided. Internal relay drivers allow direct
connection to the off-hook (RLYA) and talk/data (RLYB)
relays. The talk/data relay output can optionally be used
for pulse dial.
Speaker Interface
An analog speaker output (SPK) is provided with on/off
and volume control logic incorporated in the MDP. An
Hardware Interface Signals
A functional interconnect diagram showing the typical
MDP connection in a system is illustrated in Figure 2. Any
point that is active low is represented by a small circle at
the signal point.
Edge triggered inputs are denoted by a small triangle
(e.g., TDCLK). An active low signal is indicated by a tilde
preceding the signal name (e.g., ~RESET).
A clock intended to activate logic on its rising edge (low-
to-high transition) is called active low (e.g., ~RDCLK),
while a clock intended to activate logic on its falling edge
(high-to-low transition) is called active high (e.g., TDCLK).
When a clock input is associated with a small circle, the
input activates on a falling edge. If no circle is shown, the
input activates on a rising edge.
The 144-pin TQFP MDP hardware interface signals are
shown Figure 2.
The 144-pin TQFP MDP signal pin assignments are
shown Figure 3 and are listed in Table 4.
The 100-pin PQFP MDP hardware interface signals are
shown Figure 4.
The 100-pin PQFP MDP signal pin assignments are
shown Figure 5 and are listed in Table 5.
The MDP hardware interface signals are described in
Table 6.
The digital interface characteristics are defined in Table 7.
The analog interface characteristics are defined Table 8.
The power requirements are defined in Table 9.
The absolute maximum ratings are defined in Table 10.
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CONEXANT [ CONEXANT SYSTEMS, INC ]
