1.0 HDSL Systems
RS8953B/RS8953SPB
1.1 HTU Applications
HDSL Channel Unit
Figure 1-1 illustrates how an HDSL Terminal Unit (HTU) transports standard
T1/E1 signals. T1/E1 transceivers convert T1/E1 interface signals into a Pulse
Code Multiplexed (PCM) channel of clock, serial data, and optional frame sync.
ZipWire transceivers convert 2B1Q line signals to HDSL channels of clock, serial
data, and quat sync. The RS8953B translates between PCM and HDSL by
performing PCM timeslot and HDSL payload routing, data scrambling and
descrambling, overhead insertion and extraction, clock synchronization and clock
synthesis. The Microprocessor Unit (MPU) configures devices for the intended
application, manages overhead protocol, and monitors real-time performance.
Figure 1-1. HTU Block Diagram
HDSL
Channel 1
ZipWire Transceiver
PCM Channel
CH1
T1/E1
Transceiver
RS8953B
HDSL
Channel Unit
HDSL
Channel 2
ZipWire Transceiver
CH2
MPU Bus
HDSL
MPU
Channel 3
ZipWire Transceiver
CH3
1.1.1 Repeaters
Figure 1-2 shows single pair repeaters placed in line between HDSL terminals to
extend transmission distance. RS8953B provides an internal cross-connect path
between HDSL channels 1 and 2 to support single pair repeaters.
Figure 1-2. Repeater System Block Diagram
CH2
CH1
CH3
RS8953B
PCM
1-2
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
