RS8953B/8953SPB
2.0 Pin Descriptions
HDSL Channel Unit
2.2 Signal Definitions
2.2 Signal Definitions
Table 2-2. Signal Definitions (1 of 4)
Signal
Name
I/O
Description
Microprocessor (MPU) Interface
I(1)
MPUSEL
AD[0:7]
MPU Select
Determines the type of MPU bus control signals expected during data transfers.
Intel (MPUSEL = 0) or Motorola (MPUSEL = 1) bus types are supported. RD*
and WR* signal functions are affected.
I/O(1)
Address/Data Bus
Eight multiplexed address and data signals. The address is latched on the falling
edge of ALE and selects one of 256 internal register locations (0x00-0xFF). The
data bus transfers the contents of the latched address location during the read
or write cycle.
I(1)
CS*
Chip Select
Active-low input enables MPU read and write cycles. The rising edge of CS*
completes the read or write data transfer cycle and places the address/data bus
(AD[0]–AD[7]) in a high impedance state.
I(1)
I(1)
ALE
Address Latch
Enable
Active-high input enables the address bus. The falling edge of ALE latches the
address internally.
RD*
Read Strobe
Signal function determined by MPUSEL:
MPUSEL = 0; RD* is an active low data strobe for read cycles.
MPUSEL = 1; RD* is an active low data strobe for read/write cycles.
I(1)
WR*
INTR*
RST*
Write Strobe
Signal function determined by MPUSEL:
MPUSEL = 0; WR* is an active low data strobe for write cycles.
MPUSEL = 1; WR* controls the data bus transfer direction: high during read
cycles and low during write cycles.
Interrupt Request
Reset
O
Active low, open-drain output indicates when any one or more Interrupt Request
Register (IRR) bit is high and its respective Interrupt Mask Register (IMR) bit is
low. INTR* remains active until all pending interrupts are cleared by writing 0s
to their corresponding Interrupt Clear Register (ICR) bits.
I(1)
Active low input required to initialize internal circuits after power and master
clock have been applied. All MPU registers remain accessible while reset is
active. Unless stated otherwise, reset activation does not affect the MPU register
contents.
RS8953B reset activation disables interrupts on the INTR* output by forcing
all 1s in the Interrupt Mask Register (IMR), and zeros in the TX_ERR_EN,
DPLL_ERR_EN, and RX_ERR_EN bits.
RS8953B reset activation disables auxiliary channels by forcing zeros in all
TAUX_EN and RAUX_EN bits.
To facilitate system upgrades from prototype Bt8953EPF, RS8953B reset
activation also forces zeros in those command register bits which do not exist
on Bt8953EPF, but were added on RS8953B.
N8953BDSB
Conexant
2-7
CONEXANT [ CONEXANT SYSTEMS, INC ]
