Functional Block Diagram
SPI_DEBUG
I
2
C
PIO Serial Flash
UART
R G B
USB
XTAL
AIO[0]
SPI
(Debug)
3.3V
PIO Port
DMA ports
Bluetooth Modem
DMA ports
ep
te
m
be
r2
7,
I C/SPI
Master
/Slave
2
Serial Flash
Interface
UART
4Mbps
LED PWM
Control and
Output
USB v2.0
Full-speed
Clock
Generation
,S
Bluetooth
Baseband
20
13
TX
AUX ADC
rid
System
RAM
ay
RX
Bluetooth Radio
and Balun
BT_RF
CSR8635 QFN Data Sheet
-F
n
.c
High-quality ADC
LINE/MIC_AN
LINE/MIC_AP
LINE_BN
LINE_BP
SPKR_LN
SPKR_LP
SPKR_RN
SPKR_RP
VDD_AUDIO
VDD_AUDIO_DRV
nt
.c
o
Memory
Management
Unit
m
High-quality ADC
DMA ports
Audio
Interface
xc
el
p
oi
High-quality DAC
High-quality DAC
ROM
.z
ho
u
-e
ke
ve
n
Voltage / Temperature
Monitor
Switch
MIC Bias
MIC_BIAS
in
gb
o
PIO Port
PMU
Interface
and
BIST
Engine
0.85V to
1.2V
Low-voltage
VDD_DIG
Linear
Regulator
SENSE
VBAT
1.35V
Low-voltage
VDD_ANA
Linear
Regulator
SENSE
PM
DM1
DM2
80MHz DSP
80MHz MCU
PCM1 / I S
2
ed
VM Accelerator
(MPU)
1.35V
Low-voltage
VDD_AUX
Linear
Regulator
SENSE
SENSE
VBAT_SENSE
fo
rq
1.8V
Switch-
mode
Regulator
SENSE
1.35V
Switch-
mode
Regulator
SENSE
Bypass
LDO
Li-ion
Charger
CHG_EXT
VCHG
Pr
ep
ar
Production Information
© Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
G-TW-0012958.3.2
Digital Audio
VREGIN_DIG
VDD_DIG
VDD_BT_RADIO
VDD_ANA
VDD_AUX_1V8
VDD_AUX
LXL_1V8
SMPS_1V8_SENSE
LX_1V35
SMPS_1V35_SENSE
3V3_USB
Page 5 of 105
CS-303725-DSP5
www.csr.com
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