CY22801
Universal Programmable Clock Generator
(UPCG)
Features
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Benefits
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Integrated Phase-Locked Loop (PLL)
Field Programmable
Input Frequency Range:
❐
Crystal: 8 to 30 MHz
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CLKIN: 1 to 133 MHz
LVCMOS Output Frequency:
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1 to 200 MHz (Commercial Grade)
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1 to 166.6 MHz (Industrial Grade)
Low Jitter, High Accuracy Outputs
3.3V Operation
Commercial and Industrial Temperature Ranges
8-Pin SOIC Package
Inventory of only one device, CY22801, used in various
applications
In-house programming of sample and prototype quantities is
made available using the CY36800 InstaClock kit
Input and output frequencies are customized to suit your needs
High-performance PLL is tailored for multiple applications
Critical timing requirements met in complex system designs
Application compatibility enabled
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Logic Block Diagram
XIN/CLKIN
XTAL
OSC
CLKA
PLL
OUTPUT
DIVIDERS
CLKB
CLKC
XOUT
Pin Configuration
Figure 1. CY22801 8-Pin SOIC
XIN/CLKIN
VDD
NC
VSS
1
2
3
4
8
7
6
5
XOUT
CLKC
CLKA
CLKB
Table 1. Pin Definition
Name
XIN
VDD
NC
VSS
CLKB
CLKA
CLKC
XOUT
Pin Number
1
2
3
4
5
6
7
8
Description
Reference Input: Crystal or External Clock
3.3V Voltage Supply
No Connect; leave this pin floating
Ground
Clock Output B
Clock Output A
Clock Output C
Reference Output: Connect to external crystal. When the reference is an external clock signal
(applied to pin 1), this pin is not used and must be left floating.
Cypress Semiconductor Corporation
Document #: 001-15571 Rev. *B
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198 Champion Court
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San Jose
,
CA 95134-1709
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408-943-2600
Revised June 26, 2009
CYPRESS [ CYPRESS SEMICONDUCTOR ]
