2
CY29972
3.3V, 125-MHz Multi-Output Zero Delay Buffer
Features
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Output frequency up to 125 MHz
12 Clock outputs: frequency configurable
350 ps max. output-to-output skew
Configurable output disable
Two reference clock inputs for dynamic toggling
Oscillator or crystal reference input
Spread-spectrum-compatible
Glitch-free output clocks transitioning
3.3V power supply
Pin-compatible with MPC972
Industrial temperature range: –40°C to +85°C
52-pin TQFP package
Table 1. Frequency Table
[1]
VC0_SEL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FB_SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FB_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FB_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F
VC0
8x
12x
16x
20x
16x
24x
32x
40x
4x
6x
8x
10x
8x
12x
16x
20x
Note:
1. x = the reference input frequency, 200 MHz < F
VCO
< 480 MHz.
Block Diagram
XIN
XOUT
VCO_SEL
PLL_EN
REF_SEL
D Q
TCLK0
TCLK1
TCLK_SEL
FB_IN
D Q
Sync
Frz
0
1
Phase
Detector
LPF
VCO
0
1
Sync
Frz
QA0
QA1
QA2
QA3
QB0
QB1
FB_SEL2
QB2
QB3
Pin Configuration
52 51 50 49 48 47 46 45 44 43 42 41 40
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
XIN
XOUT
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
VCO_SEL
SELA0
SELA1
SELB0
SELB1
VDDC
VDDC
QA0
QA1
QA2
QA3
VSS
CY29972
VSS
MR#/OE
Power-On
Reset
SELA(0,1)
SELB(0,1)
SELC(0,1)
FB_SEL(0,1)
SCLK
SDATA
INV_CLK
2
2
2
2
/4, /6, /8, /10
Sync Pulse
Data Generator
D Q
/2
0
1
D Q
D Q
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
D Q
Sync
Frz
QC0
QC1
14 15 16 17 18 19 20 21 22 23 24 25 26
Sync
Frz
Sync
Frz
Sync
Frz
QC2
INV_CLK
VSS
QC3
VDDC
QC2
SELC1
SELC0
QC1
VDDC
QC0
VSS
SYNC
FB_SEL1
QC3
FB_OUT
SYNC
Output Disable
Circuitry
12
Cypress Semiconductor Corporation
Document #: 38-07290 Rev. *A
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3901 North First Street
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San Jose
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CA 95134
• 408-943-2600
December 22, 2002
CYPRESS [ CYPRESS SEMICONDUCTOR ]
