CY62128EV30 MoBL
®
1-Mbit (128 K × 8) Static RAM
1-Mbit (128 K × 8) Static RAM
Features
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Functional Description
The CY62128EV30
is a high performance CMOS static RAM
module organized as 128 K words by 8-bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE
1
HIGH or CE
2
LOW). The
eight input and output pins (I/O
0
through I/O
7
) are placed in a
high impedance state when the device is deselected (CE
1
HIGH
or CE
2
LOW), the outputs are disabled (OE HIGH), or a write
operation is in progress (CE
1
LOW and CE
2
HIGH and WE
LOW).
To write to the device, take chip enable (CE
1
LOW and CE
2
HIGH) and write enable (WE) inputs LOW. Data on the eight I/O
pins is then written into the location specified on the address pin
(A
0
through A
16
).
To read from the device, take chip enable (CE
1
LOW and CE
2
HIGH) and output enable (OE) LOW while forcing write enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
Very high speed: 45 ns
Temperature ranges:
❐
Industrial: –40 °C to +85 °C
Wide voltage range: 2.2 V to 3.6 V
Pin compatible with CY62128DV30
Ultra low standby power
❐
Typical standby current: 1 µA
❐
Maximum standby current: 4 µA
Ultra low active power
❐
Typical active current: 1.3 mA at f = 1 MHz
Easy memory expansion with CE
1
, CE
2,
and OE features
Automatic power-down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Offered in Pb-free 32-pin SOIC, 32-pin thin small outline
package (TSOP) I, and 32-pin shrunk thin small outline
package (STSOP) packages
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Logic Block Diagram
CE1
CE2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
WE
OE
INPUT BUFFER
I/O 0
I/O 1
SENSE AMPS
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
ROW DECODER
128K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
I/O 7
A12
A14
Note
1. For best practice recommendations, refer to the Cypress application note
“System Design Guidelines”
at
http://www.cypress.com.
A13
A15
A16
Cypress Semiconductor Corporation
Document #: 38-05579 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 6, 2011
CYPRESS [ CYPRESS SEMICONDUCTOR ]
