CY62256V
Switching Characteristics
Over the Operating Range
[7]
CY62256V-70
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[8, 9]
WE HIGH to Low-Z
[8]
10
70
60
60
0
0
50
30
0
25
10
100
90
90
0
0
80
60
0
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8, 9]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[8, 9]
CY62256V25-100
Min.
100
Max.
Unit
ns
100
10
100
75
5
50
10
50
0
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
70
Max.
70
10
70
35
5
25
10
25
0
70
CE LOW to Power-up
CE HIGH to Power-down
Notes:
7. Test conditions assume signal transition time of 5 ns or less timing reference levels of V
CC
/2, input pulse levels of 0 to V
CC
, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05057 Rev. *D
Page 6 of 13
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