CY7C008/009
CY7C018/01964K/128K x 8/9 Dual-Port Static RAM
CY7C008/009
CY7C018/019
64K/128K x 8/9 Dual-Port Static RAM
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 64K x 8 organization (CY7C008)
• 128K x 8 organization (CY7C009)
• 64K x 9 organization (CY7C018)
• 128K x 9 organization (CY7C019)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12
/15/20 ns
• Low operating power
—
Active: I
CC
= 180 mA (typical)
— Standby: I
SB3
= 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
Logic Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
CE
L
CE
R
R/W
R
CE
0R
CE
1R
OE
R
8/9
8/9
I/O
0L
–I/O
7/8L
I/O
Control
I/O
Control
I/O
0R
–I/O
7/8R
A
0L
–A
15/16L
16/17
Address
Decode
16/17
True Dual-Ported
RAM Array
Address
Decode
16/17
16/17
A
0R
–A
15/16R
A
0L
–A
15/16L
CE
L
OE
L
R/W
L
SEM
L
Interrupt
Semaphore
Arbitration
A
0R
–A
15/16R
CE
R
OE
R
R/W
R
SEM
R
BUSY
L
INT
L
M/S
Notes:
1.
2.
3.
4.
See page 6 for Load Conditions.
I/O
0
–I/O
7
for x8 devices; I/O
0
–I/O
8
for x9 devices.
A
0
–A
15
for 64K devices; A
0
–A
16
for 128K.
BUSY is an output in master mode and an input in slave mode.
BUSY
R
INT
R
Cypress Semiconductor Corporation
Document #: 38-06041 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised June 22, 2004
CYPRESS [ CYPRESS SEMICONDUCTOR ]
