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CY7C028V-20AC 参数 Datasheet PDF下载

CY7C028V-20AC图片预览
型号: CY7C028V-20AC
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 32K / 64K X 16/18双端口静态RAM [3.3V 32K/64K x 16/18 Dual-Port Static RAM]
分类和应用:
文件页数/大小: 18 页 / 237 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C027V/028V
CY7C037V/038V
AC Test Loads and Waveforms
3.3V
3.3V
R1 = 590Ω
OUTPUT
C = 30 pF
R2 = 435Ω
V
TH
= 1.4V
OUTPUT
C = 30 pF
R
TH
= 250Ω
R1 = 590Ω
OUTPUT
C = 5 pF
R2 = 435Ω
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0V
GND
10%
3 ns
90%
90%
10%
3 ns
(c) Three-State Delay (Load 2)
(Used for t
LZ
, t
HZ
, t
HZWE
, & t
LZWE
including scope and jig)
Switching Characteristics
Over the Operating Range
[11]
CY7C037V/038V
-15
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE[12]
t
DOE
t
LZOE[13, 14, 15]
t
HZOE[13, 14, 15]
t
LZCE[13, 14, 15]
t
HZCE[13, 14, 15]
t
PU[15]
t
PD[15]
t
ABE[12]
Write Cycle
t
WC
t
SCE[12]
t
AW
t
HA
t
SA[12]
t
PWE
t
SD
Write Cycle Time
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
Data Set-Up to Write End
15
12
12
0
0
12
10
20
16
16
0
0
17
12
25
20
20
0
0
22
15
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
0
15
15
3
10
0
20
20
3
10
3
12
0
25
25
3
15
10
3
12
3
15
15
15
3
20
12
3
15
20
20
3
25
13
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-20
Max.
Min.
-25
Max.
Unit
Notes:
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OI
/I
OH
and 30-pF load capacitance.
12. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
SCE
time.
13. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
14. Test conditions used are Load 2.
15. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading
port, refer to Read Timing with Busy waveform.
Document #: 38-06078 Rev. *A
Page 7 of 18