CY7C164
CY7C166
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
R2
255
Ω
R1 481
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255
Ω
C164–5
R1 481
Ω
ALL INPUT PULSES
3.0V
GND
10%
90%
90%
10%
< 5 ns
C164–6
< 5 ns
THÉVENIN EQUIVALENT
167
Ω
OUTPUT
1.73V
Switching Characteristics
Over the Operating Range
[5]
7C164-15
7C166-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Output Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
[8]
7C164-20
7C166-20
Min.
20
Max.
7C164-25
7C166-25
Min.
25
Max.
7C164-35
7C166-35
Min.
35
Max.
Unit
ns
35
5
35
15
3
12
5
15
0
20
25
25
25
0
0
20
15
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
Description
Min.
15
Max.
15
3
15
7C166
7C166
7C166
3
8
0
15
15
12
12
0
0
12
10
0
5
7
20
15
15
0
0
15
10
0
5
0
3
8
5
10
3
5
20
5
20
10
3
8
5
8
0
20
20
20
20
0
0
15
10
0
5
7
25
25
12
10
10
20
WRITE CYCLE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[6, 7]
7
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
for any given device. These parameters are guaranteed by design and not 100% tested.
7. t
HZCE
and t
HZWE
are specified with C
L
= 5 pF as in part (b) in AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05025 Rev. **
Page 3 of 9
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