CY7C187
AC Test Loads and Waveforms
R1 329
Ω
(480
Ω
MIL)
R1 329
Ω
(480
Ω
MIL)
ALL INPUT PULSES
3.0V
R2 202
Ω
(R1 255
Ω
MIL)
GND
10%
90%
90%
10%
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
5V
OUTPUT
R2 202
Ω
5 pF
(R1 255
Ω
MIL)
INCLUDING
JIG AND
SCOPE
≤
5 ns
≤
5 ns
C187–5
(a)
(b)
C187–4
THÉ VENIN EQUIVALENT
OUTPUT
167
Ω
125
Ω
1.73V
OUTPUT
1.90V
Military
Commercial
Switching Characteristics
Over the Operating Range
[6]
7C187-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[8]
15
12
12
0
0
12
10
0
5
7
20
15
15
0
0
15
10
0
5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Output Hold from Address Change
CE LOW to Data Valid
CE LOW to Low Z
[7]
CE HIGH to High Z
[7, 8]
CE LOW to Power Up
CE HIGH to Power Down
0
15
3
8
0
20
3
15
5
8
15
15
5
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C187-20
Min.
Max.
Unit
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
for any given device.
8. t
HZCE
and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05044 Rev. **
Page 3 of 9
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