CY7C245A
2K x 8 Reprogrammable Registered PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
—
15-ns address set-up
—
10-ns clock to output
• Low power
—
330 mW (commercial) for -25 ns
—
660 mW (military)
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered registers
• Programmable asynchronous register (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP
• 5V
±10%
V
CC
, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
Logic Block Diagram
INIT
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
CP
COLUMN
ADDRESS
ADDRESS
DECODER
PROGRAMMABLE
INITIALIZE WORD
ROW
ADDRESS
PROGRAMMABLE
ARRAY
MULTIPLEXER
O
7
Functional Description
The CY7C245A is a high-performance, 2K x 8, electrically
programmable, read-only memory packaged in a slim 300-mil
plastic or hermetic DIP. The ceramic package may be
equipped with an erasure window; when exposed to UV light
the PROM is erased and can then be reprogrammed. The
memory cells utilize proven EPROM floating-gate technology
and byte-wide intelligent programming algorithms.
The CY7C245A replaces bipolar devices and offers the advan-
tages of lower power, reprogrammability, superior perfor-
mance and high programming yield. The EPROM cell requires
only 12.5V for the supervoltage, and low current requirements
allow gang programming. The EPROM cells allow each
memory location to be tested 100%, because each location is
written into, erased, and repeatedly exercised prior to encap-
sulation. Each PROM is also tested for AC performance to
guarantee that after customer programming the product will
meet AC specification limits.
The CY7C245A has an asynchronous initialize function (INIT).
This function acts as a 2049th 8-bit word loaded into the
on-chip register. It is user programmable with any desired
word, or may be used as a PRESET or CLEAR function on the
outputs. INIT is triggered by a low level, not an edge.
Pin Configurations
DIP Top View
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
8
A
9
A
10
INIT
E/E
S
CP
O
7
O
6
O
5
O
4
O
3
O
6
O
8-BIT
EDGE-
TRIGGERED
REGISTER
O
O
3
5
4
O
O
O
0
2
1
E/E
S
CP
D
C
Q
PROGRAMMABLE
MULTIPLEXER
A
4
A
3
A
2
A
1
A
0
NC
O
0
4 3 2 1 282726
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
121314151617
O1
O2
GND
NC
O3
O4
O5
A5
A6
A7
NC
V
CC
A8
A9
LCC/PLCC (Opaque only) Top View
A
10
INIT
E/E
S
CP
NC
O
7
O
6
Selection Guide
7C245A-15
Minimum Address Set-up Time
Maximum Clock to Output
Maximum Operating Current Standard
Commercial
Military
15
10
120
7C245A-18
18
12
120
120
7C245A-25
25
12
90
120
7C245A-35
35
15
90
120
Unit
ns
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 38-04007 Rev. *D
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised November 4, 2003
CYPRESS [ CYPRESS SEMICONDUCTOR ]
