CY7C4255
CY7C4265
8K/16K x 18 Deep Sync FIFOs
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 8K x 18 (CY7C4255)
• 16K x 18 (CY7C4265)
• 0.5 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power — I
CC
= 45 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL compatible
• Retransmit function
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 64-pin TQFP and 64-pin STQFP
• Pin-compatible density upgrade to CY7C42X5 family
• Pin-compatible density upgrade to
IDT72205/15/25/35/45
• Pb-Free Packages Available
Functional Description
The CY7C4255/65 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can
be cascaded to increase FIFO depth. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and commu-
nications buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a Free-Running Clock (WCLK) and a Write
Enable pin (WEN). When WEN is asserted, data is written into the
FIFO on the rising edge of the WCLK signal. While WEN is held
active, data is continually written into the FIFO on each cycle. The
output port is controlled in a similar manner by a free-running Read
Clock (RCLK) and a Read Enable pin (REN). In addition, the
CY7C4255/65 have an Output Enable pin (OE). The read and write
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write appli-
cations. Clock frequencies up to 100 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the Cascade Input (WXI,
RXI), Cascade Output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to V
SS
and the FL pin of all the remaining
devices should be tied to V
CC
.
Logic Block Diagram
D
0–17
INPUT
REGISTER
WCLK
WEN
WRITE
CONTROL
FLAG
PROGRAM
REGISTER
RAM
ARRAY
8K x 18
16K x 18
WRITE
POINTER
FLAG
LOGIC
FF
EF
PAE
PAF
SMODE
READ
POINTER
RS
RESET
LOGIC
FL/RT
WXI
WXO/HF
RXI
RXO
EXPANSION
LOGIC
THREE–STATE
OUTPUT REGISTER
Q
0–17
OE
READ
CONTROL
RCLK
REN
Cypress Semiconductor Corporation
Document #: 38-06004 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised August 2, 2005
CYPRESS [ CYPRESS SEMICONDUCTOR ]
