CY7C4281V/CY7C4291V CY7C4261V/CY7C4271V16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs
Features
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO)
memories
• 16K × 9 (CY7C4261V)
• 32K × 9 (CY7C4271V)
• 64K × 9 (CY7C4281V)
• 128K × 9 (CY7C4291V)
• 0.35-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power
— I
CC
= 25 mA
— I
SB
= 4 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and programmable Almost Empty and
Almost Full status flags
• Output Enable (OE) pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width- Expansion capability
• Pin-compatible 3.3V solutions for CY7C4261/71/81/91
• Pin-compatible density upgrade to CY7C42X1V family
• Pb-Free Packages Available
Functional Description
The CY7C4261/71/81/91V are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71/81/91V are pin-compatible to the
CY7C42x1V Synchronous FIFO family. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1 and WEN2/LD are held active, data is continually
written into the FIFO on each WCLK cycle. The output port is
controlled in a similar manner by a free-running read clock
(RCLK) and two read enable pins (REN1, REN2). In addition,
the CY7C4261/71/81/91V has an output enable pin (OE). The
read (RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion
is possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow
of data.
LogicBlock Diagram
D
0–8
INPUT
REGISTER
Pin Configuration
PLCC
Top View
D
2
D
3
D
4
D
5
D
6
D
7
D
8
WCLK WEN1 WEN2/LD
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
FLAG
LOGIC
READ
POINTER
EF
PAE
PAF
FF
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
WRITE
POINTER
RESET
LOGIC
Dual Port
RAM Array
16K/32K
64K/128K
x9
5
6
7
8
9
10
11
12
13
4 3 2 1 32 31 30
29
28
25
24
23
22
21
14 15 16 17 18 19 20
EF
FF
Q
0
Q
1
Q
2
Q
3
Q
4
CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V
27
26
RS
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
RS
THREE-STATE
OUTPUT REGISTER
OE
Q
0–8
READ
CONTROL
RCLK REN1 REN2
Cypress Semiconductor Corporation
Document #: 38-06013 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised August 2, 2005
CYPRESS [ CYPRESS SEMICONDUCTOR ]
