16K/32K x 9 Deep Sync FIFOsCY7C4271CY7C4261
CY7C4261
CY7C4271
16K/32K x 9 Deep Sync FIFOs
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 16K × 9 (CY7C4261)
• 32K × 9 (CY7C4271)
• 0.5-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power — I
CC
= 35 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL-compatible
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width-Expansion Capability
• Military temp SMD Offering – CY7C4271-15LMB
• 32-pin PLCC/LCC and 32-pin TQFP
• Pin-compatible density upgrade to CY7C42X1 family
• Pin-compatible density upgrade to
IDT72201/11/21/31/41/51
• Pb-Free Packages Available
Functional Description
The CY7C4261/71 are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can
be cascaded to increase FIFO width. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the CY7C4261/71
has an output enable pin (OE). The read (RCLK) and write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable. Depth expansion is possible using one enable
input for system control, while the other enable is controlled by
expansion logic to direct the flow of data.
Logic Block Diagram
D
0–8
INPUT
REGISTER
Pin Configuration
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
EF
PAE
PAF
FF
PLCC/LCC
Top View
4 3 2 1 32 31 30
29
5
28
6
27
7
8
CY7C4261
26
9
25
CY7C4271
24
10
11
23
22
12
21
13
14 15 16 17 18 19 20
EF
FF
Q
0
Q
1
Q
2
D
2
D
3
D
4
D
5
D
6
D
7
D
8
WCLK WEN1 WEN2/LD
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
FLAG
LOGIC
RAM
ARRAY
16K x 9
32K x 9
RS
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
WRITE
POINTER
READ
POINTER
D
1
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
D
0
PAF
PAE
RS
RESET
LOGIC
THREE-STATE
OUTPUT REGISTER
OE
Q
0–8
READ
CONTROL
GND
REN1
RCLK
REN2
CY7C4261
CY7C4271
RCLK REN1 REN2
OE
EF
FF
Q
0
Q
1
Q
2
Cypress Semiconductor Corporation
Document #: 38-06015 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised August 2, 2005
Q
3
Q
4
RS
D
2
D
3
D
4
D
5
D
6
D
7
D
8
TQFP
Top View
Q
3
Q
4
CYPRESS [ CYPRESS SEMICONDUCTOR ]
