CY7C63413C
CY7C63513C
CY7C63613C
Table 5. Port 3 Data
Addr: 0x03
P3[7]
R/W
P3[6]
R/W
P3[5]
R/W
Port 3 Data
P3[4]
R/W
P3[3]
R/W
P3[2]
R/W
P3[1]
R/W
P3[0]
R/W
Table 6. DAC Port Data
Addr: 0x30
DAC Port Data
Low current outputs
0.2 mA to 1.0 mA typical
DAC[7]
R/W
DAC[6]
R/W
DAC[5]
R/W
DAC[4]
R/W
DAC[3]
R/W
DAC[2]
R/W
High current outputs
3.2 mA to 16 mA typical
DAC[1]
R/W
DAC[0]
R/W
Port 3 has eight GPIO pins. Port 3 (8 bits) can be configured
as inputs with internal pull-ups, open drain outputs, or tradi-
tional CMOS outputs. An open drain output is also a high-
impedance input. Port 3 offers high current drive with a typical
current sink capability of 12 mA. The internal pull-up resistors
are typically 7 kΩ.
Note:
Special care should be exercised with any unused GPIO
data bits. An unused GPIO data bit, either a pin on the chip or
a port bit that is not bonded on a particular package, must not
be left floating when the device enters the suspend state. If a
GPIO data bit is left floating, the leakage current caused by the
floating bit may violate the suspend current limitation specified
by the USB Specification. If a ‘1’ is written to the unused data
bit and the port is configured with open drain outputs, the
unused data bit will be in an indeterminate state. Therefore, if
an unused port bit is programmed in open-drain mode, it must
be written with a ‘0.’ Notice that the CY7C63613C will always
require that data bits P1[7:4], P2[7:0], P3[3:0] and DAC[7:0] be
written with a ‘0’.
During reset, all of the bits in the GPIO to a default configu-
ration of Open Drain output, positive interrupt polarity for all
GPIO ports.
GPIO Interrupt Enable Ports
During a reset, GPIO interrupts are disabled by clearing all of
the GPIO interrupt enable ports. Writing a “1” to a GPIO
Interrupt Enable bit enables GPIO interrupts from the corre-
sponding input pin.
GPIO Configuration Port
Every GPIO port can be programmed as inputs with internal
pull-ups, open drain outputs, and traditional CMOS outputs. In
addition, the interrupt polarity for each port can be pro-
grammed. With positive interrupt polarity, a rising edge (“0” to
“1”) on an input pin causes an interrupt. With negative polarity,
a falling edge (“1” to “0”) on an input pin causes an interrupt.
As shown in the table below, when a GPIO port is configured
with CMOS outputs, interrupts from that port are disabled. The
GPIO Configuration Port register provides two bits per port to
program these features. The possible port configurations are
as shown in
Table 7. Port 0 Interrupt Enable
Addr: 0x04
P0[7]
W
P0[6]
W
P0[5]
W
Port 0 Interrupt Enable
P0[4]
W
P0[3]
W
P0[2]
W
P0[1]
W
P0[0]
W
Table 8. Port 1 Interrupt Enable
Addr: 0x05
P1[7]
W
P1[6]
W
P1[5]
W
Port 1 Interrupt Enable
P1[4]
W
P1[3]
W
P1[2]
W
P1[1]
W
P1[0]
W
Table 9. Port 2 Interrupt Enable
Addr: 0x06
P2[7]
W
P2[6]
W
P2[5]
W
Port 2 Interrupt Enable
P2[4]
W
P2[3]
W
P2[2]
W
P2[1]
W
P2[0]
W
Table 10.Port 3 Interrupt Enable
Addr: 0x07
P3[7]
W
P3[6]
W
P3[5]
W
Port 3 Interrupt Enable
P3[4]
W
P3[3]
W
P3[2]
W
P3[1]
W
P3[0]
W
Document #: 38-08027 Rev. *B
Page 12 of 32
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