FOR
FOR
enCoRe™ USB CY7C63722/23
CY7C63743
VCC
2
GPIO
Mode
SPI Bypass (P0.5–P0.7 only)
Q3
Q1
(=1 if SPI inactive, or for non-SPI pins)
Data
Internal
14 kΩ
Out
Data Bus
Register
GPIO
Pin
Q2
Port Write
(Data Reg must be 1
for SPI outputs)
Threshold Select
Port Read
To Capture Timers (P0.0, P0.1)
and SPI (P0.4–P0.7))
Interrupt
Polarity
Interrupt
Logic
To Interrupt
Controller
Interrupt
Enable
Figure 12-1. Block Diagram of GPIO Port (one pin shown)
Port 0 is an 8-bit port; Port 1 contains either 2 bits, P1.1–P1.0 in the CY7C63723, or all 8 bits, P1.7–P1.0 in the CY7C63743 parts.
Each bit can also be selected as an interrupt source for the microcontroller, as explained in Section 21.0.
The data for each GPIO pin is accessible through the Port Data register. Writes to the Port Data register store outgoing data state
for the port pins, while reads from the Port Data register return the actual logic value on the port pins, not the Port Data register
contents.
Each GPIO pin is configured independently. The driving state of each GPIO pin is determined by the value written to the pin’s
Data Register and by two associated pin’s Mode0 and Mode1 bits.
The Port 0 Data Register is shown in Figure 12-2, and the Port 1 Data Register is shown in Figure 12-3. The Mode0 and Mode1
bits for the two GPIO ports are given in Figure 12-4 through Figure 12-7.
Bit #
Bit Name
Read/Write
Reset
7
6
5
4
3
2
1
0
P0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Figure 12-2. Port 0 Data (Address 0x00)
Bit [7:0]: P0[7:0]
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
Bit #
Bit Name
Notes
7
6
5
4
3
2
1
0
P1
Pins 7:2 only in CY7C63743
Pins 1:0 in all parts
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Figure 12-3. Port 1 Data (Address 0x01)
Document #: 38-08022 Rev. **
Page 19 of 58
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